snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE, AC97_GP_DRSS_MASK, AC97_GP_DRSS_78);
                if ((snd_ac97_read(ac97, AC97_GENERAL_PURPOSE) & AC97_GP_DRSS_MASK) == AC97_GP_DRSS_78)
                        ac97->flags |= AC97_DOUBLE_RATE;
+               /* restore to slots 10/11 to avoid the confliction with surrounds */
+               snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE, AC97_GP_DRSS_MASK, 0);
        }
        if (ac97->ext_id & AC97_EI_VRA) {       /* VRA support */
                snd_ac97_determine_rates(ac97, AC97_PCM_FRONT_DAC_RATE, 0, &ac97->rates[AC97_RATES_FRONT_DAC]);
 
                                     AC97_EA_DRA, dbl ? AC97_EA_DRA : 0);
        snd_ac97_update(ac97, reg, tmp & 0xffff);
        snd_ac97_read(ac97, reg);
+       if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) {
+               /* Intel controllers require double rate data to be put in
+                * slots 7+8
+                */
+               snd_ac97_update_bits(ac97, AC97_GENERAL_PURPOSE,
+                                    AC97_GP_DRSS_MASK,
+                                    dbl ? AC97_GP_DRSS_78 : 0);
+               snd_ac97_read(ac97, AC97_GENERAL_PURPOSE);
+       }
        return 0;
 }