drm/radeon: fix pixcache and purge/cache flushing registers

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index 8f664af9c4a4f50d7ecd905b81fa39dd15dde89f..a72c703224832023f909d2a8d11a8a9b19059f5e 100644 (file)
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -1346,7 +1346,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* Guess by Vladimir.
  * Set to 0A before 3D operations, set to 02 afterwards.
  */
-#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C
+/*#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C*/
 #       define R300_RB3D_DSTCACHE_UNKNOWN_02             0x00000002
 #       define R300_RB3D_DSTCACHE_UNKNOWN_0A             0x0000000A
 

diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index fc0820c2b4b4b1dbcfa1d7d875204b8f26a92eef..8fce12e73403b2a1d76d68749a21bb5f892a74da 100644 (file)
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -161,16 +161,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 
        dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-       tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
-       tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-       RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
-
-       for (i = 0; i < dev_priv->usec_timeout; i++) {
-               if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
-                     & RADEON_RB3D_DC_BUSY)) {
-                       return 0;
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
+               tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
+               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+               RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+
+               for (i = 0; i < dev_priv->usec_timeout; i++) {
+                       if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
+                             & RADEON_RB3D_DC_BUSY)) {
+                               return 0;
+                       }
+                       DRM_UDELAY(1);
+               }
+       } else {
+               /* 3D */
+               tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
+               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+               RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
+
+               /* 2D */
+               tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
+               tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+               RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+
+               for (i = 0; i < dev_priv->usec_timeout; i++) {
+                       if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
+                         & RADEON_RB3D_DC_BUSY)) {
+                               return 0;
+                       }
+                       DRM_UDELAY(1);
                }
-               DRM_UDELAY(1);
        }
 
 #if RADEON_FIFO_DEBUG

diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 3063b0fa512fc642bbcbf9168f1b4f6c625dbede..5e6f4612adbaa6a174a0458beedf78e33ce8c9a9 100644 (file)
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -659,11 +659,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #      define RADEON_RB3D_ZC_FREE              (1 << 2)
 #      define RADEON_RB3D_ZC_FLUSH_ALL         0x5
 #      define RADEON_RB3D_ZC_BUSY              (1 << 31)
+#define R300_ZB_ZCACHE_CTLSTAT                  0x4f18
+#      define R300_ZC_FLUSH                    (1 << 0)
+#      define R300_ZC_FREE                     (1 << 1)
+#      define R300_ZC_FLUSH_ALL                0x3
+#      define R300_ZC_BUSY                     (1 << 31)
 #define RADEON_RB3D_DSTCACHE_CTLSTAT   0x325c
 #      define RADEON_RB3D_DC_FLUSH             (3 << 0)
 #      define RADEON_RB3D_DC_FREE              (3 << 2)
 #      define RADEON_RB3D_DC_FLUSH_ALL         0xf
 #      define RADEON_RB3D_DC_BUSY              (1 << 31)
+#define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
+#      define R300_RB3D_DC_FINISH              (1 << 4)
 #define RADEON_RB3D_ZSTENCILCNTL       0x1c2c
 #      define RADEON_Z_TEST_MASK               (7 << 4)
 #      define RADEON_Z_TEST_ALWAYS             (7 << 4)
@@ -1178,23 +1185,43 @@ do {                                                                    \
 } while (0)
 
 #define RADEON_FLUSH_CACHE() do {                                      \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
-       OUT_RING( RADEON_RB3D_DC_FLUSH );                               \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
+               OUT_RING(RADEON_RB3D_DC_FLUSH);                         \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_DC_FLUSH);                         \
+       }                                                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {                                      \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
-       OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );                           \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
+               OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+       }                                                               \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {                                     \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );        \
-       OUT_RING( RADEON_RB3D_ZC_FLUSH );                               \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_ZC_FLUSH);                         \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));        \
+               OUT_RING(R300_ZC_FLUSH);                                \
+       }                                                               \
 } while (0)
 
 #define RADEON_PURGE_ZCACHE() do {                                     \
-       OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );        \
-       OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );                           \
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+               OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
+               OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);                     \
+       } else {                                                        \
+               OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+               OUT_RING(R300_ZC_FLUSH_ALL);                            \
+       }                                                               \
 } while (0)
 
 /* ================================================================