RTL_GIGA_MAC_VER_03 = 0x02,
        RTL_GIGA_MAC_VER_04 = 0x03,
        RTL_GIGA_MAC_VER_05 = 0x04,
-       RTL_GIGA_MAC_VER_11 = 0x0b,
-       RTL_GIGA_MAC_VER_12 = 0x0c,
+       RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
+       RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
        RTL_GIGA_MAC_VER_13 = 0x0d,
        RTL_GIGA_MAC_VER_14 = 0x0e,
        RTL_GIGA_MAC_VER_15 = 0x0f
 
 static void rtl_hw_start_8168(struct net_device *dev)
 {
-       rtl_hw_start_8169(dev);
+       struct rtl8169_private *tp = netdev_priv(dev);
+       void __iomem *ioaddr = tp->mmio_addr;
+
+       RTL_W8(Cfg9346, Cfg9346_Unlock);
+
+       RTL_W8(EarlyTxThres, EarlyTxThld);
+
+       rtl_set_rx_max_size(ioaddr);
+
+       tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
+
+       RTL_W16(CPlusCmd, tp->cp_cmd);
+
+       RTL_W16(IntrMitigate, 0x0000);
+
+       rtl_set_rx_tx_desc_registers(tp, ioaddr);
+
+       RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
+       rtl_set_rx_tx_config_registers(tp);
+
+       RTL_W8(Cfg9346, Cfg9346_Lock);
+
+       RTL_R8(IntrMask);
+
+       RTL_W32(RxMissed, 0);
+
+       rtl_set_rx_mode(dev);
+
+       RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 }
 
 static void rtl_hw_start_8101(struct net_device *dev)