static int iwl4965_alive_notify(struct iwl_priv *priv)
 {
        u32 a;
-       int i = 0;
        unsigned long flags;
        int ret;
+       int i, chan;
 
        spin_lock_irqsave(&priv->lock, flags);
 
        iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
                        priv->scd_bc_tbls.dma >> 10);
 
+       /* Enable DMA channel */
+       for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
+               iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
+                               FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
+                               FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
+
        /* Disable chain mode for all queues */
        iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
 
                                 (1 << priv->hw_params.max_txq_num) - 1);
 
        /* Activate all Tx DMA/FIFO channels */
-       priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
+       priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
 
        iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 
 
 static int iwl5000_alive_notify(struct iwl_priv *priv)
 {
        u32 a;
-       int i = 0;
        unsigned long flags;
        int ret;
+       int i, chan;
 
        spin_lock_irqsave(&priv->lock, flags);
 
 
        iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
                       priv->scd_bc_tbls.dma >> 10);
+
+       /* Enable DMA channel */
+       for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
+               iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
+                               FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
+                               FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
+
        iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
                IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
        iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 
        iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
                             txq->q.dma_addr >> 8);
 
-       /* Enable DMA channel, using same id as for TFD queue */
-       iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
-                       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
-                       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
-
        iwl_release_nic_access(priv);
        spin_unlock_irqrestore(&priv->lock, flags);