[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag

Define it for i386 too.

This is a synthetic flag that signifies that the CPU's TSC runs
at a constant P state invariant frequency.

Fix up the logic on x86-64/i386 to set it on all known CPUs.
Use the AMD defined bit to set it on future AMD CPUs.

Cc: venkatesh.pallipadi@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index e7697e077f6bce7895a560cfdc049be3a914f8f4..4397f61705e2b7d230e9dc32e609b1cd5646ecd9 100644 (file)
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -216,6 +216,11 @@ static void __init init_amd(struct cpuinfo_x86 *c)
                        c->x86_max_cores = 1;
        }
 
+       if (cpuid_eax(0x80000000) >= 0x80000007) {
+               if (cpuid_edx(0x80000007) & (1<<8))
+                       set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
+       }
+
 #ifdef CONFIG_X86_HT
        /*
         * On a AMD dual core setup the lower bits of the APIC id
@@ -233,6 +238,7 @@ static void __init init_amd(struct cpuinfo_x86 *c)
                       cpu, c->x86_max_cores, cpu_core_id[cpu]);
        }
 #endif
+
 }
 
 static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)

diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 5e2da704f0faa8200fa744e39d8ffb86dd860542..8c0120186b9fc6ba5ef5ea932df98098667135d2 100644 (file)
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -183,10 +183,13 @@ static void __devinit init_intel(struct cpuinfo_x86 *c)
        }
 #endif
 
-       if (c->x86 == 15) 
+       if (c->x86 == 15)
                set_bit(X86_FEATURE_P4, c->x86_capability);
        if (c->x86 == 6) 
                set_bit(X86_FEATURE_P3, c->x86_capability);
+       if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
+               (c->x86 == 0x6 && c->x86_model >= 0x0e))
+               set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 }
 
 

diff --git a/arch/i386/kernel/cpu/proc.c b/arch/i386/kernel/cpu/proc.c
index 6d91b274589c7fff2bef8e0d35aaa90c41de71a6..66592fad2bfe1c53d12c79c5131bc84524b33fd7 100644 (file)
--- a/arch/i386/kernel/cpu/proc.c
+++ b/arch/i386/kernel/cpu/proc.c
@@ -40,7 +40,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                /* Other (Linux-defined) */
                "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
                NULL, NULL, NULL, NULL,
-               NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+               "constant_tsc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 

diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 754a05f9b4dbcdf8fd142fe61c01459a03bb0ea8..d9c1c3bd61505cc9833aa00123fc2bb825c56d09 100644 (file)
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -1032,7 +1032,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
        if (c->x86 == 15)
                c->x86_cache_alignment = c->x86_clflush_size * 2;
-       if (c->x86 >= 15)
+       if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
+           (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
        c->x86_max_cores = intel_num_cpu_cores(c);
 
@@ -1273,7 +1274,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                "tm",
                "stc"
                "?",
-               "constant_tsc",
+               /* nothing */   /* constant_tsc - moved to flags */
        };
 
 

diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index ff1187e80c32f4a657a28c1b5ab4e4ec98dd5550..c4ec2a4d8fdf701e33b0879b1ff4830b963f7ad4 100644 (file)
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -69,6 +69,7 @@
 #define X86_FEATURE_K7         (3*32+ 5) /* Athlon */
 #define X86_FEATURE_P3         (3*32+ 6) /* P3 */
 #define X86_FEATURE_P4         (3*32+ 7) /* P4 */
+#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */