release_region(hwif->dma_base, 8);
        if (hwif->extra_ports)
                release_region(hwif->extra_base, hwif->extra_ports);
-       if (hwif->dma_base2)
-               release_region(hwif->dma_base, 8);
        return 1;
 }
 
        }
 
        if(hwif->mate)
-               hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
+               hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base;
        else
                hwif->dma_master = base;
-       if (hwif->dma_base2) {
-               if (!request_region(hwif->dma_base2, ports, hwif->name))
-               {
-                       printk(" -- Error, secondary ports in use.\n");
-                       release_region(base, ports);
-                       if (hwif->extra_ports)
-                               release_region(hwif->extra_base, hwif->extra_ports);
-                       return 1;
-               }
-       }
        return 0;
 }
 
 
        ide_hwif_t *hwif = HWIF(drive);
        u64 dma_base = hwif->dma_base;
        int dma_stat = 0;
-       unsigned long *ending_dma = (unsigned long *) hwif->dma_base2;
+       unsigned long *ending_dma = ide_get_hwifdata(hwif);
 
        hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
 
 {
        void __iomem *virt_dma_base;
        int num_ports = sizeof (ioc4_dma_regs_t);
+       void *pad;
 
        printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
               dma_base, dma_base + num_ports - 1);
 
        hwif->sg_max_nents = IOC4_PRD_ENTRIES;
 
-       hwif->dma_base2 = (unsigned long)
-               pci_alloc_consistent(hwif->pci_dev,
-                                    IOC4_IDE_CACHELINE_SIZE,
-                                    (dma_addr_t *) &(hwif->dma_status));
+       pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
+                                  (dma_addr_t *) &(hwif->dma_status));
 
-       if (!hwif->dma_base2)
-               goto dma_base2alloc_failure;
-
-       return;
+       if (pad) {
+               ide_set_hwifdata(hwif, pad);
+               return;
+       }
 
-dma_base2alloc_failure:
        pci_free_consistent(hwif->pci_dev,
                            IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
                            hwif->dmatable_cpu, hwif->dmatable_dma);
        hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4);
 
        /* Address of the Ending DMA */
-       memset((unsigned int *) hwif->dma_base2, 0, IOC4_IDE_CACHELINE_SIZE);
+       memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
        ending_dma_addr = cpu_to_le32(hwif->dma_status);
        hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4);
 
 
        unsigned long   dma_status;     /* dma status register */
        unsigned long   dma_vendor3;    /* dma vendor 3 register */
        unsigned long   dma_prdtable;   /* actual prd table address */
-       unsigned long   dma_base2;      /* extended base addr for dma ports */
 
        unsigned long   config_data;    /* for use by chipset-specific code */
        unsigned long   select_data;    /* for use by chipset-specific code */