sh: Fix up L2 cache probe.

SH7723 is the first hard silicon to implement the L2, and unsurprisingly,
does the precise inverse of what the specification alleges. XOR the
URAM/L2 size bits to get back in line with the existing parsing logic.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6ea87af7247e70aa6532025eb3c49d11742a69b2..ebceb0dadff58fc70026f646fe507b48f29c6a2d 100644 (file)
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
         * SH-4A's have an optional PIPT L2.
         */
        if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+               /* Bug if we can't decode the L2 info */
+               BUG_ON(!(cvr & 0xf));
+
+               /* Silicon and specifications have clearly never met.. */
+               cvr ^= 0xf;
+
                /*
                 * Size calculation is much more sensible
                 * than it is for the L1.