static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned                gpmc_cs_map;
 
-static u32 gpmc_base;
+static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
 
        unsigned long rate = clk_get_rate(gpmc_l3_clk);
 
        if (rate == 0) {
-               printk(KERN_WARNING "gpmc_l3_clk no enabled\n");
+               printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
                return 0;
        }
 
 void __init gpmc_init(void)
 {
        u32 l;
+       char *ck;
 
        if (cpu_is_omap24xx()) {
-               gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
+               ck = "core_l3_ck";
                if (cpu_is_omap2420())
-                       gpmc_base = OMAP2_IO_ADDRESS(OMAP2420_GPMC_BASE);
-               else if (cpu_is_omap2430())
-                       gpmc_base = OMAP2_IO_ADDRESS(OMAP243X_GPMC_BASE);
+                       l = OMAP2420_GPMC_BASE;
+               else
+                       l = OMAP34XX_GPMC_BASE;
        } else if (cpu_is_omap34xx()) {
-               gpmc_l3_clk = clk_get(NULL, "gpmc_fck");
-               gpmc_base = OMAP2_IO_ADDRESS(OMAP34XX_GPMC_BASE);
+               ck = "gpmc_fck";
+               l = OMAP34XX_GPMC_BASE;
+       }
+
+       gpmc_l3_clk = clk_get(NULL, ck);
+       if (IS_ERR(gpmc_l3_clk)) {
+               printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
+               return -ENODEV;
+       }
+
+       gpmc_base = ioremap(l, SZ_4K);
+       if (!gpmc_base) {
+               clk_put(gpmc_l3_clk);
+               printk(KERN_ERR "Could not get GPMC register memory\n");
+               return -ENOMEM;
        }
 
        BUG_ON(IS_ERR(gpmc_l3_clk));