/* if ack is already set then we cannot be sure
                         * we are referring to the correct operation
                         */
-                       BUG_ON(depend_tx->ack);
+                       BUG_ON(async_tx_test_ack(depend_tx));
                        if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
                                panic("%s: DMA_ERROR waiting for depend_tx\n",
                                        __func__);
 
         * otherwise poll for completion
         */
        if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
-               intr_tx = device->device_prep_dma_interrupt(chan);
+               intr_tx = device->device_prep_dma_interrupt(chan, 0);
        else
                intr_tx = NULL;
 
                 * 2/ dependencies are 1:1 i.e. two transactions can
                 * not depend on the same parent
                 */
-               BUG_ON(depend_tx->ack || depend_tx->next || tx->parent);
+               BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
+                      tx->parent);
 
                /* the lock prevents async_tx_run_dependencies from missing
                 * the setting of ->next when ->parent != NULL
                if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
                        device = NULL;
 
-               tx = device ? device->device_prep_dma_interrupt(chan) : NULL;
+               tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
        } else
                tx = NULL;
 
                        /* if ack is already set then we cannot be sure
                         * we are referring to the correct operation
                         */
-                       BUG_ON(depend_tx->ack);
+                       BUG_ON(async_tx_test_ack(depend_tx));
                        if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
                                panic("%s: DMA_ERROR waiting for depend_tx\n",
                                        __func__);
 
                                /* if ack is already set then we cannot be sure
                                 * we are referring to the correct operation
                                 */
-                               BUG_ON(depend_tx->ack);
+                               BUG_ON(async_tx_test_ack(depend_tx));
                                if (dma_wait_for_async_tx(depend_tx) ==
                                        DMA_ERROR)
                                        panic("%s: DMA_ERROR waiting for "
 
 
        dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
        dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
-       tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, 0);
+       tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
+                                        DMA_CTRL_ACK);
 
        if (!tx) {
                dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
                return -ENOMEM;
        }
 
-       tx->ack = 1;
        tx->callback = NULL;
        cookie = tx->tx_submit(tx);
 
 
        dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
        dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
-       tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, 0);
+       tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
+                                        DMA_CTRL_ACK);
 
        if (!tx) {
                dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
                return -ENOMEM;
        }
 
-       tx->ack = 1;
        tx->callback = NULL;
        cookie = tx->tx_submit(tx);
 
        dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
        dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
                                DMA_FROM_DEVICE);
-       tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, 0);
+       tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
+                                        DMA_CTRL_ACK);
 
        if (!tx) {
                dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
                return -ENOMEM;
        }
 
-       tx->ack = 1;
        tx->callback = NULL;
        cookie = tx->tx_submit(tx);
 
 
 }
 
 static struct dma_async_tx_descriptor *
-fsl_dma_prep_interrupt(struct dma_chan *chan)
+fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
 {
        struct fsl_dma_chan *fsl_chan;
        struct fsl_desc_sw *new;
        }
 
        new->async_tx.cookie = -EBUSY;
-       new->async_tx.ack = 0;
+       new->async_tx.flags = flags;
 
        /* Insert the link descriptor to the LD ring */
        list_add_tail(&new->node, &new->async_tx.tx_list);
                        set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
 
                new->async_tx.cookie = 0;
-               new->async_tx.ack = 1;
+               async_tx_ack(&new->async_tx);
 
                prev = new;
                len -= copy;
                list_add_tail(&new->node, &first->async_tx.tx_list);
        } while (len);
 
-       new->async_tx.ack = 0; /* client is in control of this ack */
+       new->async_tx.flags = flags; /* client is in control of this ack */
        new->async_tx.cookie = -EBUSY;
 
        /* Set End-of-link to the last link descriptor of new list*/
        async_tx_ack(tx3);
 
        /* Interrupt tx test */
-       tx1 = fsl_dma_prep_interrupt(chan);
+       tx1 = fsl_dma_prep_interrupt(chan, 0);
        async_tx_ack(tx1);
        cookie = fsl_dma_tx_submit(tx1);
 
 
        u32 copy;
        size_t len;
        dma_addr_t src, dst;
-       int orig_ack;
+       unsigned long orig_flags;
        unsigned int desc_count = 0;
 
        /* src and dest and len are stored in the initial descriptor */
        len = first->len;
        src = first->src;
        dst = first->dst;
-       orig_ack = first->async_tx.ack;
+       orig_flags = first->async_tx.flags;
        new = first;
 
        spin_lock_bh(&ioat_chan->desc_lock);
        do {
                copy = min_t(size_t, len, ioat_chan->xfercap);
 
-               new->async_tx.ack = 1;
+               async_tx_ack(&new->async_tx);
 
                hw = new->hw;
                hw->size = copy;
        }
 
        new->tx_cnt = desc_count;
-       new->async_tx.ack = orig_ack; /* client is in control of this ack */
+       new->async_tx.flags = orig_flags; /* client is in control of this ack */
 
        /* store the original values for use in later cleanup */
        if (new != first) {
        u32 copy;
        size_t len;
        dma_addr_t src, dst;
-       int orig_ack;
+       unsigned long orig_flags;
        unsigned int desc_count = 0;
 
        /* src and dest and len are stored in the initial descriptor */
        len = first->len;
        src = first->src;
        dst = first->dst;
-       orig_ack = first->async_tx.ack;
+       orig_flags = first->async_tx.flags;
        new = first;
 
        /*
        do {
                copy = min_t(size_t, len, ioat_chan->xfercap);
 
-               new->async_tx.ack = 1;
+               async_tx_ack(&new->async_tx);
 
                hw = new->hw;
                hw->size = copy;
        }
 
        new->tx_cnt = desc_count;
-       new->async_tx.ack = orig_ack; /* client is in control of this ack */
+       new->async_tx.flags = orig_flags; /* client is in control of this ack */
 
        /* store the original values for use in later cleanup */
        if (new != first) {
                new->len = len;
                new->dst = dma_dest;
                new->src = dma_src;
-               new->async_tx.ack = 0;
+               new->async_tx.flags = flags;
                return &new->async_tx;
        } else
                return NULL;
                new->len = len;
                new->dst = dma_dest;
                new->src = dma_src;
-               new->async_tx.ack = 0;
+               new->async_tx.flags = flags;
                return &new->async_tx;
        } else
                return NULL;
                                 * a completed entry, but not the last, so clean
                                 * up if the client is done with the descriptor
                                 */
-                               if (desc->async_tx.ack) {
+                               if (async_tx_test_ack(&desc->async_tx)) {
                                        list_del(&desc->node);
                                        list_add_tail(&desc->node,
                                                      &ioat_chan->free_desc);
        desc->hw->size = 0;
        desc->hw->src_addr = 0;
        desc->hw->dst_addr = 0;
-       desc->async_tx.ack = 1;
+       async_tx_ack(&desc->async_tx);
        switch (ioat_chan->device->version) {
        case IOAT_VER_1_2:
                desc->hw->next = 0;
 
        /* the client is allowed to attach dependent operations
         * until 'ack' is set
         */
-       if (!desc->async_tx.ack)
+       if (!async_tx_test_ack(&desc->async_tx))
                return 0;
 
        /* leave the last descriptor in the chain
                        "this_desc: %#x next_desc: %#x ack: %d\n",
                        iter->async_tx.cookie, iter->idx, busy,
                        iter->async_tx.phys, iop_desc_get_next_desc(iter),
-                       iter->async_tx.ack);
+                       async_tx_test_ack(&iter->async_tx));
                prefetch(_iter);
                prefetch(&_iter->async_tx);
 
 
                                /* pre-ack all but the last descriptor */
                                if (num_slots != slots_per_op)
-                                       iter->async_tx.ack = 1;
-                               else
-                                       iter->async_tx.ack = 0;
+                                       async_tx_ack(&iter->async_tx);
 
                                list_add_tail(&iter->chain_node, &chain);
                                alloc_tail = iter;
 }
 
 static struct dma_async_tx_descriptor *
-iop_adma_prep_dma_interrupt(struct dma_chan *chan)
+iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
 {
        struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
        struct iop_adma_desc_slot *sw_desc, *grp_start;
                grp_start = sw_desc->group_head;
                iop_desc_init_interrupt(grp_start, iop_chan);
                grp_start->unmap_len = 0;
+               sw_desc->async_tx.flags = flags;
        }
        spin_unlock_bh(&iop_chan->lock);
 
                iop_desc_set_memcpy_src_addr(grp_start, dma_src);
                sw_desc->unmap_src_cnt = 1;
                sw_desc->unmap_len = len;
+               sw_desc->async_tx.flags = flags;
        }
        spin_unlock_bh(&iop_chan->lock);
 
                iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
                sw_desc->unmap_src_cnt = 1;
                sw_desc->unmap_len = len;
+               sw_desc->async_tx.flags = flags;
        }
        spin_unlock_bh(&iop_chan->lock);
 
                iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
                sw_desc->unmap_src_cnt = src_cnt;
                sw_desc->unmap_len = len;
+               sw_desc->async_tx.flags = flags;
                while (src_cnt--)
                        iop_desc_set_xor_src_addr(grp_start, src_cnt,
                                                  dma_src[src_cnt]);
                        __func__, grp_start->xor_check_result);
                sw_desc->unmap_src_cnt = src_cnt;
                sw_desc->unmap_len = len;
+               sw_desc->async_tx.flags = flags;
                while (src_cnt--)
                        iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
                                                       dma_src[src_cnt]);
        src_dma = dma_map_single(dma_chan->device->dev, src,
                                IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
        tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
-                                     IOP_ADMA_TEST_SIZE, 1);
+                                     IOP_ADMA_TEST_SIZE,
+                                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 
        cookie = iop_adma_tx_submit(tx);
        iop_adma_issue_pending(dma_chan);
-       async_tx_ack(tx);
        msleep(1);
 
        if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
                dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
                                           0, PAGE_SIZE, DMA_TO_DEVICE);
        tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
-                                  IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, 1);
+                                  IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
+                                  DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 
        cookie = iop_adma_tx_submit(tx);
        iop_adma_issue_pending(dma_chan);
-       async_tx_ack(tx);
        msleep(8);
 
        if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
                                           DMA_TO_DEVICE);
        tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
                                        IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
-                                       &zero_sum_result, 1);
+                                       &zero_sum_result,
+                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 
        cookie = iop_adma_tx_submit(tx);
        iop_adma_issue_pending(dma_chan);
-       async_tx_ack(tx);
        msleep(8);
 
        if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
        /* test memset */
        dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
                        PAGE_SIZE, DMA_FROM_DEVICE);
-       tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, 1);
+       tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
+                                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 
        cookie = iop_adma_tx_submit(tx);
        iop_adma_issue_pending(dma_chan);
-       async_tx_ack(tx);
        msleep(8);
 
        if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
                                           DMA_TO_DEVICE);
        tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
                                        IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
-                                       &zero_sum_result, 1);
+                                       &zero_sum_result,
+                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 
        cookie = iop_adma_tx_submit(tx);
        iop_adma_issue_pending(dma_chan);
-       async_tx_ack(tx);
        msleep(8);
 
        if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
                grp_start = sw_desc->group_head;
 
                list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
-               sw_desc->async_tx.ack = 1;
+               async_tx_ack(&sw_desc->async_tx);
                iop_desc_init_memcpy(grp_start, 0);
                iop_desc_set_byte_count(grp_start, iop_chan, 0);
                iop_desc_set_dest_addr(grp_start, iop_chan, 0);
        if (sw_desc) {
                grp_start = sw_desc->group_head;
                list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
-               sw_desc->async_tx.ack = 1;
+               async_tx_ack(&sw_desc->async_tx);
                iop_desc_init_null_xor(grp_start, 2, 0);
                iop_desc_set_byte_count(grp_start, iop_chan, 0);
                iop_desc_set_dest_addr(grp_start, iop_chan, 0);
 
 #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
 
 /**
- * enum dma_prep_flags - DMA flags to augment operation preparation
+ * enum dma_ctrl_flags - DMA flags to augment operation preparation,
+ *     control completion, and communicate status.
  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
  *     this transaction
+ * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
+ *     acknowledges receipt, i.e. has has a chance to establish any
+ *     dependency chains
  */
-enum dma_prep_flags {
+enum dma_ctrl_flags {
        DMA_PREP_INTERRUPT = (1 << 0),
+       DMA_CTRL_ACK = (1 << 1),
 };
 
 /**
  * ---dma generic offload fields---
  * @cookie: tracking cookie for this transaction, set to -EBUSY if
  *     this tx is sitting on a dependency list
- * @ack: the descriptor can not be reused until the client acknowledges
- *     receipt, i.e. has has a chance to establish any dependency chains
+ * @flags: flags to augment operation preparation, control completion, and
+ *     communicate status
  * @phys: physical address of the descriptor
  * @tx_list: driver common field for operations that require multiple
  *     descriptors
  */
 struct dma_async_tx_descriptor {
        dma_cookie_t cookie;
-       int ack;
+       enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
        dma_addr_t phys;
        struct list_head tx_list;
        struct dma_chan *chan;
                struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
                unsigned long flags);
        struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
-               struct dma_chan *chan);
+               struct dma_chan *chan, unsigned long flags);
 
        enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
                        dma_cookie_t cookie, dma_cookie_t *last,
 static inline void
 async_tx_ack(struct dma_async_tx_descriptor *tx)
 {
-       tx->ack = 1;
+       tx->flags |= DMA_CTRL_ACK;
+}
+
+static inline int
+async_tx_test_ack(struct dma_async_tx_descriptor *tx)
+{
+       return tx->flags & DMA_CTRL_ACK;
 }
 
 #define first_dma_cap(mask) __first_dma_cap(&(mask))