.rate           = 32000,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &propagate_rate,
 };
 
        .name           = "osc_ck",
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_PROPAGATES,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable         = &omap2_enable_osc_ck,
        .disable        = &omap2_disable_osc_ck,
        .recalc         = &omap2_osc_clk_recalc,
        .parent         = &osc_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                ALWAYS_ENABLED | RATE_PROPAGATES,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &omap2_sys_clk_recalc,
 };
 
        .rate           = 54000000,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &propagate_rate,
 };
 
        .dpll_data      = &dpll_dd,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_PROPAGATES | ALWAYS_ENABLED,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &omap2_dpllcore_recalc,
        .set_rate       = &omap2_reprogram_dpllcore,
 };
        .rate           = 96000000,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
        .enable         = &omap2_clk_fixed_enable,
        .rate           = 54000000,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
        .enable         = &omap2_clk_fixed_enable,
        .parent         = &func_54m_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                RATE_PROPAGATES | OFFSET_GR_MOD,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
        .init           = &omap2_init_clksel_parent,
        .parent         = &sys_clkout_src,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
        .clksel         = sys_clkout_clksel,
        .name           = "gpios_fck",
        .parent         = &func_32k_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
        .recalc         = &followparent_recalc,
 };
 
+/* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
 static struct clk mpu_wdt_ick = {
        .name           = "mpu_wdt_ick",
        .parent         = &l4_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .clkdm          = { .name = "core_l4_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
        .recalc         = &followparent_recalc,
 };
 
+/* aka WDT2 */
 static struct clk mpu_wdt_fck = {
        .name           = "mpu_wdt_fck",
        .parent         = &func_32k_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
        .recalc         = &followparent_recalc,
        .recalc         = &followparent_recalc,
 };
 
+/* REVISIT: parent is really wu_l4_iclk */
 static struct clk wdt1_ick = {
        .name           = "wdt1_ick",
        .parent         = &l4_ck,
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-       .clkdm          = { .name = "core_l4_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
        .recalc         = &followparent_recalc,
 
        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
 
        .init           = &omap2_init_clk_clkdm,
        .parent         = &omap_32k_fck,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .name           = "wkup_l4_ick",
        .parent         = &sys_ck,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
-/* XXX This clock no longer exists in 3430 TRM rev F */
 static struct clk gpt12_ick = {
        .name           = "gpt12_ick",
        .parent         = &wkup_l4_ick,
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
 
        .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
-       .clkdm          = { .name = "wkup_clkdm" },
+       .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };