[ARM] Remove MODE_(SVC|IRQ|FIQ|USR) and DEFAULT_FIQ

DEFAULT_FIQ was entirely unused.  MODE_* are just redefinitions
of *_MODE.  Use *_MODE instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index adf62e5eaad7a7f8ba120a76b9c39c00bc64d458..2af7e44218af77d3f5f4864710818f45f89bcec3 100644 (file)
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -39,7 +39,7 @@
        __INIT
        .type   stext, %function
 ENTRY(stext)
-       msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
+       msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
                                                @ and irqs disabled
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 04f7344e356a30b12b5b7b7b4d8695c222960d55..330b9476c398d63856c7daa8ab5aaf2378f0d667 100644 (file)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -71,7 +71,7 @@
        __INIT
        .type   stext, %function
 ENTRY(stext)
-       msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
+       msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
                                                @ and irqs disabled
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
@@ -104,7 +104,7 @@ ENTRY(secondary_startup)
         * the processor type - there is no need to check the machine type
         * as it has already been validated by the primary processor.
         */
-       msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+       msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type
        movs    r10, r5                         @ invalid processor?

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index c9862688ff3d6694f6e812717bdb41eeb2e84cc6..0650bed3b96ea3536e5a68ddaec7667d8b33a611 100644 (file)
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -189,7 +189,7 @@ ENTRY(pxa_cpu_suspend)
        .data
        .align 5
 ENTRY(pxa_cpu_resume)
-       mov     r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC   @ set SVC, irqs off
+       mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE   @ set SVC, irqs off
        msr     cpsr_c, r0
 
        ldr     r0, sleep_save_sp               @ stack phys addr

diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 5f6761ed96b207cdcae72642b693a52c0ca94242..dc27167f4d595eb53d271afec92c4fc5a56c0303 100644 (file)
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -128,7 +128,7 @@ s3c2410_sleep_save_phys:
        */
 
 ENTRY(s3c2410_cpu_resume)
-       mov     r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC
+       mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
        msr     cpsr_c, r0
 
        @@ load UART to allow us to print the two characters for

diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 2fa1e289d1776e470ec3c5e42509bc20a5c72c96..5a84062f92af903fb96c3ab043cd50ada1006ad7 100644 (file)
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -177,7 +177,7 @@ sa1110_sdram_controller_fix:
        .data
        .align 5
 ENTRY(sa1100_cpu_resume)
-       mov     r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+       mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
        msr     cpsr_c, r0                      @ set SVC, irqs off
 
        ldr     r0, sleep_save_sp               @ stack phys addr

diff --git a/arch/arm/nwfpe/entry26.S b/arch/arm/nwfpe/entry26.S
index 51940a96d6a6bb74bb885add92157fdf0f98c984..3e6fb5d21d6452dc6e6751e544ee20d3a6d4bcd8 100644 (file)
--- a/arch/arm/nwfpe/entry26.S
+++ b/arch/arm/nwfpe/entry26.S
@@ -26,7 +26,7 @@
 It is called from the kernel with code similar to this:
 
        mov     fp, #0
-       teqp    pc, #PSR_I_BIT | MODE_SVC
+       teqp    pc, #PSR_I_BIT | SVC_MODE
        ldr     r4, .LC2
        ldr     pc, [r4]                @ Call FP module USR entry point
 

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index b97cb3e1ba72c949ca2d8be0b368c7e4af0948e6..fce8328208258bcd64cae06279608a8d4008f347 100644 (file)
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -55,13 +55,6 @@
 #define PLD(code...)
 #endif
 
-#define MODE_USR       USR_MODE
-#define MODE_FIQ       FIQ_MODE
-#define MODE_IRQ       IRQ_MODE
-#define MODE_SVC       SVC_MODE
-
-#define DEFAULT_FIQ    MODE_FIQ
-
 /*
  * Enable and disable interrupts
  */