[Sorry, the previous patch was a copy/paste mistake, this one should be
better]
I have no access to the docs for this chip but I'm pretty sure the current
address of the two DIDR1 registers is wrong because it's outside the
TUSB-specific register space.  The modified address in turn has a good
chance to be correct.
Signed-off-by: Andrzej Zaborowski <balrog@zabor.org>
Acked-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 #define TUSB_PROD_TEST_RESET_VAL               0xa596
 #define TUSB_EP_FIFO(ep)                       (TUSB_FIFO_BASE + (ep) * 0x20)
 
-#define TUSB_DIDR1_LO                          0x1f8
-#define TUSB_DIDR1_HI                          0x1fc
+#define TUSB_DIDR1_LO                          (TUSB_SYS_REG_BASE + 0x1f8)
+#define TUSB_DIDR1_HI                          (TUSB_SYS_REG_BASE + 0x1fc)
 #define                TUSB_DIDR1_HI_CHIP_REV(v)               (((v) >> 17) & 0xf)
 #define                        TUSB_DIDR1_HI_REV_20            0
 #define                        TUSB_DIDR1_HI_REV_30            1