for (i = 0; i < DM_NUM_CHANNELS; i++) {
                const u64 base_val = CPHYSADDR(&page_descr[i]) |
                                     V_DM_DSCR_BASE_RINGSZ(1);
-               volatile void *base_reg =
-                       IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
+               void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
 
                __raw_writeq(base_val, base_reg);
                __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
 
        /*
         * See if the PCI bus has been configured by the firmware.
         */
-       reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
+       reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
        if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
                bcm1480_bus_status |= PCI_DEVICE_MODE;
        } else {
 
        /*
         * See if the PCI bus has been configured by the firmware.
         */
-       reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
+       reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
        if (!(reg & M_SYS_PCI_HOST)) {
                sb1250_bus_status |= PCI_DEVICE_MODE;
        } else {
 
  * independent of board/firmware
  */
 
-static volatile void *mailbox_0_set_regs[] = {
+static void *mailbox_0_set_regs[] = {
        IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
        IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
        IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
        IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 };
 
-static volatile void *mailbox_0_clear_regs[] = {
+static void *mailbox_0_clear_regs[] = {
        IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
        IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
        IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
        IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 };
 
-static volatile void *mailbox_0_regs[] = {
+static void *mailbox_0_regs[] = {
        IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
        IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
        IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
 
 #define LEDS_PHYS MLEDS_PHYS
 #endif
 
-#define setled(index, c) \
-  ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)
 void setleds(char *str)
 {
+       void *reg;
        int i;
+
        for (i = 0; i < 4; i++) {
-               if (!str[i]) {
-                       setled(i, ' ');
-               } else {
-                       setled(i, str[i]);
-               }
+               reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);
+
+               if (!str[i])
+                       writeb(' ', reg);
+               else
+                       writeb(str[i], reg);
        }
 }
-#endif
+
+#endif /* LEDS_PHYS */
 
         * Controller-specific things
         */
 
-       volatile void __iomem *sbm_base;          /* MAC's base address */
+       void __iomem            *sbm_base;          /* MAC's base address */
        sbmac_state_t    sbm_state;         /* current state */
 
        volatile void __iomem   *sbm_macenable; /* MAC Enable Register */
 
 
 #endif
 
-#define IOADDR(a) ((volatile void __iomem *)(IO_BASE + (a)))
+#define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
 
 #endif