Use the #define for ACPI_LEVEL_SENSITIVE instead of assuming
non-zero, because ACPICA 
20051021 changes its value to zero.
Also, use uniform variable names:
edge_level -> triggering
active_high_low -> polarity
Signed-off-by: Len Brown <len.brown@intel.com>
 
  * success: return IRQ number (>=0)
  * failure: return < 0
  */
-int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
+int acpi_register_gsi(u32 gsi, int triggering, int polarity)
 {
        unsigned int irq;
        unsigned int plat_gsi = gsi;
        if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
                extern void eisa_set_level_irq(unsigned int irq);
 
-               if (edge_level == ACPI_LEVEL_SENSITIVE)
+               if (triggering == ACPI_LEVEL_SENSITIVE)
                        eisa_set_level_irq(gsi);
        }
 #endif
 
 #ifdef CONFIG_X86_IO_APIC
        if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
-               plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low);
+               plat_gsi = mp_register_gsi(gsi, triggering, polarity);
        }
 #endif
        acpi_gsi_to_irq(plat_gsi, &irq);
 
 
 #define MAX_GSI_NUM    4096
 
-int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
+int mp_register_gsi (u32 gsi, int triggering, int polarity)
 {
        int                     ioapic = -1;
        int                     ioapic_pin = 0;
 
        mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 
-       if (edge_level) {
+       if (triggering == ACPI_LEVEL_SENSITIVE) {
                /*
                 * For PCI devices assign IRQs in order, avoiding gaps
                 * due to unused I/O APIC pins.
        }
 
        io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
-                   edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
-                   active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
+                   triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
+                   polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
        return gsi;
 }
 
 
  * success: return IRQ number (>=0)
  * failure: return < 0
  */
-int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
+int acpi_register_gsi(u32 gsi, int triggering, int polarity)
 {
        if (has_8259 && gsi < 16)
                return isa_irq_to_vector(gsi);
 
        return iosapic_register_intr(gsi,
-                                    (active_high_low ==
+                                    (polarity ==
                                      ACPI_ACTIVE_HIGH) ? IOSAPIC_POL_HIGH :
                                     IOSAPIC_POL_LOW,
-                                    (edge_level ==
+                                    (triggering ==
                                      ACPI_EDGE_SENSITIVE) ? IOSAPIC_EDGE :
                                     IOSAPIC_LEVEL);
 }
 
 
        mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 
-       if (triggering) {
+       if (triggering == ACPI_LEVEL_SENSITIVE) {
                /*
                 * For PCI devices assign IRQs in order, avoiding gaps
                 * due to unused I/O APIC pins.