[ARM] MX31/MX35: Add l2x0 cache support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 0589b5cd33c7be5fd08a5a59013ada0f85ce457f..44fcb6679f9a558d944847ad2f5da012d8d092ae 100644 (file)
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -22,10 +22,14 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <mach/hardware.h>
+#include <linux/err.h>
+
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
 #include <mach/common.h>
+#include <mach/hardware.h>
 
 /*!
  * @file mm.c
@@ -62,3 +66,24 @@ void __init mxc_map_io(void)
 {
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
+
+#ifdef CONFIG_CACHE_L2X0
+static int mxc_init_l2x0(void)
+{
+       void __iomem *l2x0_base;
+
+       l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
+       if (IS_ERR(l2x0_base)) {
+               printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+                               PTR_ERR(l2x0_base));
+               return 0;
+       }
+
+       l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+
+       return 0;
+}
+
+arch_initcall(mxc_init_l2x0);
+#endif
+

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d490f3773c01c12aec0b1266d55aa8b92193649b..0d8581f112113e1a00f08913b86a72c19b642e50 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -704,7 +704,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
-       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP
+       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
+                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31
        default y
        select OUTER_CACHE
        help