Remove L2 info from id.c

Now we have Catalin's cache patch applied, which should eventually
hit mainline at some point.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a526c0fc628d94553dfef5d23ce0773be9127aa2..d375ba22d12207f9e87b7a28807cd7bf1d6de413 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -264,32 +264,6 @@ void __init omap2_check_revision(void)
 
 }
 
-#ifdef CONFIG_ARCH_OMAP3
-/*
- * OMAP3 has L2 cache which has to be enabled by bootloader.
- */
-static int __init omap3_check_l2cache(void)
-{
-       u32 val;
-
-       if (class < OMAP3430_REV_ES1_0)
-               return -ENODEV;
-
-       /* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
-       asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
-
-       if ((val & 0x2) == 0)
-               printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
-                      "your bootloader. L2 off results in performance loss\n");
-       else
-               pr_info("OMAP3 L2 cache enabled\n");
-
-       return 0;
-}
-
-arch_initcall(omap3_check_l2cache);
-#endif /* CONFIG_ARCH_OMAP3 */
-
 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 {
        class = omap2_globals->class;