OMAP: Make dpll4_m4_ck programmable with clk_set_rate()

Filling the set_rate and round_rate fields of dpll4_m4_ck makes
this clock programmable through clk_set_rate().  This is needed
to give omapfb control over the dss1_alwon_fck rate.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 0b95fcbb51f1987d7087f739efc51f1158310c0e..1c2b49f32747d72acdb63ba75e248240c520aeec 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -879,6 +879,8 @@ static struct clk dpll4_m6_ck = {
                                PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */