#endif
 
 
+/* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+       [0] = {
+               .start  = AT91CAP9_BASE_TCB0,
+               .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91CAP9_ID_TCB,
+               .end    = AT91CAP9_ID_TCB,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91cap9_tcb_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb_resources,
+       .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has one clock and irq for all three TC channels */
+       at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
+       platform_device_register(&at91cap9_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
 /* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 {
        at91_add_device_rtt();
        at91_add_device_watchdog();
+       at91_add_device_tc();
        return 0;
 }
 
 
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+       [0] = {
+               .start  = AT91RM9200_BASE_TCB0,
+               .end    = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91RM9200_ID_TC0,
+               .end    = AT91RM9200_ID_TC0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT91RM9200_ID_TC1,
+               .end    = AT91RM9200_ID_TC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT91RM9200_ID_TC2,
+               .end    = AT91RM9200_ID_TC2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91rm9200_tcb0_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb0_resources,
+       .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+       [0] = {
+               .start  = AT91RM9200_BASE_TCB1,
+               .end    = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91RM9200_ID_TC3,
+               .end    = AT91RM9200_ID_TC3,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT91RM9200_ID_TC4,
+               .end    = AT91RM9200_ID_TC4,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT91RM9200_ID_TC5,
+               .end    = AT91RM9200_ID_TC5,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91rm9200_tcb1_device = {
+       .name           = "atmel_tcb",
+       .id             = 1,
+       .resource       = tcb1_resources,
+       .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has a separate clock and irq for each TC channel */
+       at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
+       at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
+       at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
+       platform_device_register(&at91rm9200_tcb0_device);
+
+       at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
+       at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
+       at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
+       platform_device_register(&at91rm9200_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
 /* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
 {
        at91_add_device_rtc();
        at91_add_device_watchdog();
+       at91_add_device_tc();
        return 0;
 }
 
 
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+       [0] = {
+               .start  = AT91SAM9260_BASE_TCB0,
+               .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9260_ID_TC0,
+               .end    = AT91SAM9260_ID_TC0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT91SAM9260_ID_TC1,
+               .end    = AT91SAM9260_ID_TC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT91SAM9260_ID_TC2,
+               .end    = AT91SAM9260_ID_TC2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9260_tcb0_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb0_resources,
+       .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+       [0] = {
+               .start  = AT91SAM9260_BASE_TCB1,
+               .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9260_ID_TC3,
+               .end    = AT91SAM9260_ID_TC3,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT91SAM9260_ID_TC4,
+               .end    = AT91SAM9260_ID_TC4,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT91SAM9260_ID_TC5,
+               .end    = AT91SAM9260_ID_TC5,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9260_tcb1_device = {
+       .name           = "atmel_tcb",
+       .id             = 1,
+       .resource       = tcb1_resources,
+       .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has a separate clock and irq for each TC channel */
+       at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
+       at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
+       at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
+       platform_device_register(&at91sam9260_tcb0_device);
+
+       at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
+       at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
+       at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
+       platform_device_register(&at91sam9260_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
 /* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 {
        at91_add_device_rtt();
        at91_add_device_watchdog();
+       at91_add_device_tc();
        return 0;
 }
 
 
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+       [0] = {
+               .start  = AT91SAM9261_BASE_TCB0,
+               .end    = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9261_ID_TC0,
+               .end    = AT91SAM9261_ID_TC0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT91SAM9261_ID_TC1,
+               .end    = AT91SAM9261_ID_TC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT91SAM9261_ID_TC2,
+               .end    = AT91SAM9261_ID_TC2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9261_tcb_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb_resources,
+       .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has a separate clock and irq for each TC channel */
+       at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
+       at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
+       at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
+       platform_device_register(&at91sam9261_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
 /* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 {
        at91_add_device_rtt();
        at91_add_device_watchdog();
+       at91_add_device_tc();
        return 0;
 }
 
 
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+       [0] = {
+               .start  = AT91SAM9263_BASE_TCB0,
+               .end    = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9263_ID_TCB,
+               .end    = AT91SAM9263_ID_TCB,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9263_tcb_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb_resources,
+       .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has one clock and irq for all three TC channels */
+       at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
+       platform_device_register(&at91sam9263_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
 /* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 {
        at91_add_device_rtt();
        at91_add_device_watchdog();
+       at91_add_device_tc();
        return 0;
 }
 
 
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+       [0] = {
+               .start  = AT91SAM9RL_BASE_TCB0,
+               .end    = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91SAM9RL_ID_TC0,
+               .end    = AT91SAM9RL_ID_TC0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT91SAM9RL_ID_TC1,
+               .end    = AT91SAM9RL_ID_TC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT91SAM9RL_ID_TC2,
+               .end    = AT91SAM9RL_ID_TC2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at91sam9rl_tcb_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb_resources,
+       .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has a separate clock and irq for each TC channel */
+       at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
+       at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
+       at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
+       platform_device_register(&at91sam9rl_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
 /* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
        at91_add_device_rtc();
        at91_add_device_rtt();
        at91_add_device_watchdog();
+       at91_add_device_tc();
        return 0;
 }