pci_bus_register_of_sysfs(child_bus);
 }
 
-struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
+struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
+                                           struct device *parent)
 {
        struct device_node *node = pbm->prom_node;
        struct pci_bus *bus;
 
        printk("PCI: Scanning PBM %s\n", node->full_name);
 
-       /* XXX parent device? XXX */
-       bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
+       bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm);
        if (!bus) {
                printk(KERN_ERR "Failed to create bus for %s\n",
                       node->full_name);
 
                               "i" (ASI_PHYS_BYPASS_EC_E) \
                             : "memory")
 
-static void __init pci_fire_scan_bus(struct pci_pbm_info *pbm)
-{
-       pbm->pci_bus = pci_scan_one_pbm(pbm);
-
-       /* XXX register error interrupt handlers XXX */
-}
-
 #define FIRE_IOMMU_CONTROL     0x40000UL
 #define FIRE_IOMMU_TSBBASE     0x40008UL
 #define FIRE_IOMMU_FLUSH       0x40100UL
 }
 
 static int __init pci_fire_pbm_init(struct pci_controller_info *p,
-                                   struct device_node *dp, u32 portid)
+                                   struct of_device *op, u32 portid)
 {
        const struct linux_prom64_registers *regs;
+       struct device_node *dp = op->node;
        struct pci_pbm_info *pbm;
        int err;
 
 
        pci_fire_msi_init(pbm);
 
-       pci_fire_scan_bus(pbm);
+       pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
+
+       /* XXX register error interrupt handlers XXX */
 
        return 0;
 }
        portid = of_getintprop_default(dp, "portid", 0xff);
        for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
                if (portid_compare(pbm->portid, portid))
-                       return pci_fire_pbm_init(pbm->parent, dp, portid);
+                       return pci_fire_pbm_init(pbm->parent, op, portid);
        }
 
        err = -ENOMEM;
 
        p->pbm_B.iommu = iommu;
 
-       return pci_fire_pbm_init(p, dp, portid);
+       return pci_fire_pbm_init(p, op, portid);
 
 out_free_iommu_A:
        kfree(p->pbm_A.iommu);
 
        pci_config_write8(addr, 64);
 }
 
-static void __init psycho_scan_bus(struct pci_pbm_info *pbm)
+static void __init psycho_scan_bus(struct pci_pbm_info *pbm,
+                                  struct device *parent)
 {
        pbm_config_busmastering(pbm);
        pbm->is_66mhz_capable = 0;
-       pbm->pci_bus = pci_scan_one_pbm(pbm);
+       pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 
        /* After the PCI bus scan is complete, we can register
         * the error interrupt handlers.
 #define PSYCHO_MEMSPACE_SIZE   0x07fffffffUL
 
 static void __init psycho_pbm_init(struct pci_controller_info *p,
-                           struct device_node *dp, int is_pbm_a)
+                                  struct of_device *op, int is_pbm_a)
 {
+       struct device_node *dp = op->node;
        struct property *prop;
        struct pci_pbm_info *pbm;
 
 
        psycho_pbm_strbuf_init(pbm, is_pbm_a);
 
-       psycho_scan_bus(pbm);
+       psycho_scan_bus(pbm, &op->dev);
 }
 
 #define PSYCHO_CONFIGSPACE     0x001000000UL
 
                if (p->pbm_A.portid == upa_portid) {
                        is_pbm_a = (p->pbm_A.prom_node == NULL);
-                       psycho_pbm_init(p, dp, is_pbm_a);
+                       psycho_pbm_init(p, op, is_pbm_a);
                        return 0;
                }
        }
 
        is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
 
-       psycho_pbm_init(p, dp, is_pbm_a);
+       psycho_pbm_init(p, op, is_pbm_a);
 
        return 0;
 
 
        }
 }
 
-static void __init sabre_scan_bus(struct pci_pbm_info *pbm)
+static void __init sabre_scan_bus(struct pci_pbm_info *pbm,
+                                 struct device *parent)
 {
        static int once;
 
        }
        once++;
 
-       pbm->pci_bus = pci_scan_one_pbm(pbm);
+       pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
        if (!pbm->pci_bus)
                return;
 
 }
 
 static void __init sabre_pbm_init(struct pci_controller_info *p,
-                                 struct pci_pbm_info *pbm, struct device_node *dp)
+                                 struct pci_pbm_info *pbm, struct of_device *op)
 {
+       struct device_node *dp = op->node;
+
        pbm->name = dp->full_name;
        printk("%s: SABRE PCI Bus Module\n", pbm->name);
 
 
        pci_determine_mem_io_space(pbm);
 
-       sabre_scan_bus(pbm);
+       sabre_scan_bus(pbm, &op->dev);
 }
 
 static int __devinit sabre_probe(struct of_device *op,
        /*
         * Look for APB underneath.
         */
-       sabre_pbm_init(p, pbm, dp);
+       sabre_pbm_init(p, pbm, op);
        return 0;
 
 out_free_iommu:
 
        pci_config_write8(addr, 64);
 }
 
-static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm)
+static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm,
+                                     struct device *parent)
 {
        pbm_config_busmastering(pbm);
        pbm->is_66mhz_capable =
                (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
                 != NULL);
 
-       pbm->pci_bus = pci_scan_one_pbm(pbm);
+       pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 
        if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
                tomatillo_register_error_handlers(pbm);
 }
 
 static int __devinit schizo_pbm_init(struct pci_controller_info *p,
-                                    struct device_node *dp, u32 portid,
+                                    struct of_device *op, u32 portid,
                                     int chip_type)
 {
        const struct linux_prom64_registers *regs;
+       struct device_node *dp = op->node;
        struct pci_pbm_info *pbm;
        const char *chipset_name;
        int is_pbm_a, err;
 
        schizo_pbm_strbuf_init(pbm);
 
-       schizo_scan_bus(pbm);
+       schizo_scan_bus(pbm, &op->dev);
 
        return 0;
 }
        return (x == y);
 }
 
-static int __devinit __schizo_init(struct device_node *dp, unsigned long chip_type)
+static int __devinit __schizo_init(struct of_device *op, unsigned long chip_type)
 {
+       struct device_node *dp = op->node;
        struct pci_controller_info *p;
        struct pci_pbm_info *pbm;
        struct iommu *iommu;
        err = -ENOMEM;
        for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
                if (portid_compare(pbm->portid, portid, chip_type)) {
-                       if (schizo_pbm_init(pbm->parent, dp,
+                       if (schizo_pbm_init(pbm->parent, op,
                                            portid, chip_type))
                                goto out_err;
                        return 0;
 
        p->pbm_B.iommu = iommu;
 
-       if (schizo_pbm_init(p, dp, portid, chip_type))
+       if (schizo_pbm_init(p, op, portid, chip_type))
                goto out_free_iommu_B;
 
        return 0;
 static int __devinit schizo_probe(struct of_device *op,
                                  const struct of_device_id *match)
 {
-       return __schizo_init(op->node, (unsigned long) match->data);
+       return __schizo_init(op, (unsigned long) match->data);
 }
 
 /* The ordering of this table is very important.  Some Tomatillo
 
        .sync_sg_for_cpu                = dma_4v_sync_sg_for_cpu,
 };
 
-static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
+static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm,
+                                     struct device *parent)
 {
        struct property *prop;
        struct device_node *dp;
        dp = pbm->prom_node;
        prop = of_find_property(dp, "66mhz-capable", NULL);
        pbm->is_66mhz_capable = (prop != NULL);
-       pbm->pci_bus = pci_scan_one_pbm(pbm);
+       pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 
        /* XXX register error interrupt handlers XXX */
 }
 #endif /* !(CONFIG_PCI_MSI) */
 
 static int __init pci_sun4v_pbm_init(struct pci_controller_info *p,
-                                    struct device_node *dp, u32 devhandle)
+                                    struct of_device *op, u32 devhandle)
 {
+       struct device_node *dp = op->node;
        struct pci_pbm_info *pbm;
        int err;
 
 
        pci_sun4v_msi_init(pbm);
 
-       pci_sun4v_scan_bus(pbm);
+       pci_sun4v_scan_bus(pbm, &op->dev);
 
        return 0;
 }
 
        for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
                if (pbm->devhandle == (devhandle ^ 0x40)) {
-                       return pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
+                       return pci_sun4v_pbm_init(pbm->parent, op, devhandle);
                }
        }
 
 
        p->pbm_B.iommu = iommu;
 
-       return pci_sun4v_pbm_init(p, dp, devhandle);
+       return pci_sun4v_pbm_init(p, op, devhandle);
 
 out_free_iommu_A:
        kfree(p->pbm_A.iommu);