count = 3;
        id = my_cluster | (1UL << count);
        x86_cpu_to_log_apicid[smp_processor_id()] = id;
-       apic_write_around(APIC_DFR, APIC_DFR_CLUSTER);
+       apic_write(APIC_DFR, APIC_DFR_CLUSTER);
        val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
        val |= SET_APIC_LOGICAL_ID(id);
-       apic_write_around(APIC_LDR, val);
+       apic_write(APIC_LDR, val);
 }
 
 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
 
        num = smp_processor_id();
        id = 1UL << num;
        x86_cpu_to_log_apicid[num] = id;
-       apic_write_around(APIC_DFR, APIC_DFR_FLAT);
+       apic_write(APIC_DFR, APIC_DFR_FLAT);
        val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
        val |= SET_APIC_LOGICAL_ID(id);
-       apic_write_around(APIC_LDR, val);
+       apic_write(APIC_LDR, val);
 }
 
 static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
         * prepare target chip field
         */
        cfg = __prepare_ICR2(mask);
-       apic_write_around(APIC_ICR2, cfg);
+       apic_write(APIC_ICR2, cfg);
 
        /*
         * program the ICR
        /*
         * Send the IPI. The write to APIC_ICR fires this off.
         */
-       apic_write_around(APIC_ICR, cfg);
+       apic_write(APIC_ICR, cfg);
        local_irq_restore(flags);
 }
 
 
        /*
         * Send the IPI. The write to APIC_ICR fires this off.
         */
-       apic_write_around(APIC_ICR, cfg);
+       apic_write(APIC_ICR, cfg);
 }
 
 
                 * prepare target chip field
                 */
                cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
-               apic_write_around(APIC_ICR2, cfg);
+               apic_write(APIC_ICR2, cfg);
 
                /*
                 * program the ICR
                /*
                 * Send the IPI. The write to APIC_ICR fires this off.
                 */
-               apic_write_around(APIC_ICR, cfg);
+               apic_write(APIC_ICR, cfg);
        }
        local_irq_restore(flags);
 }