arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  37 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 /* PRM CLOCKS */
  57
  58 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  59 static struct clk omap_32k_fck = {
  60         .name           = "omap_32k_fck",
  61         .ops            = &clkops_null,
  62         .rate           = 32768,
  63         .flags          = RATE_FIXED,
  64 };
  65
  66 static struct clk secure_32k_fck = {
  67         .name           = "secure_32k_fck",
  68         .ops            = &clkops_null,
  69         .rate           = 32768,
  70         .flags          = RATE_FIXED,
  71 };
  72
  73 /* Virtual source clocks for osc_sys_ck */
  74 static struct clk virt_12m_ck = {
  75         .name           = "virt_12m_ck",
  76         .ops            = &clkops_null,
  77         .rate           = 12000000,
  78         .flags          = RATE_FIXED,
  79 };
  80
  81 static struct clk virt_13m_ck = {
  82         .name           = "virt_13m_ck",
  83         .ops            = &clkops_null,
  84         .rate           = 13000000,
  85         .flags          = RATE_FIXED,
  86 };
  87
  88 static struct clk virt_16_8m_ck = {
  89         .name           = "virt_16_8m_ck",
  90         .ops            = &clkops_null,
  91         .rate           = 16800000,
  92         .flags          = RATE_FIXED,
  93 };
  94
  95 static struct clk virt_19_2m_ck = {
  96         .name           = "virt_19_2m_ck",
  97         .ops            = &clkops_null,
  98         .rate           = 19200000,
  99         .flags          = RATE_FIXED,
 100 };
 101
 102 static struct clk virt_26m_ck = {
 103         .name           = "virt_26m_ck",
 104         .ops            = &clkops_null,
 105         .rate           = 26000000,
 106         .flags          = RATE_FIXED,
 107 };
 108
 109 static struct clk virt_38_4m_ck = {
 110         .name           = "virt_38_4m_ck",
 111         .ops            = &clkops_null,
 112         .rate           = 38400000,
 113         .flags          = RATE_FIXED,
 114 };
 115
 116 static const struct clksel_rate osc_sys_12m_rates[] = {
 117         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 118         { .div = 0 }
 119 };
 120
 121 static const struct clksel_rate osc_sys_13m_rates[] = {
 122         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 123         { .div = 0 }
 124 };
 125
 126 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 127         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 128         { .div = 0 }
 129 };
 130
 131 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 132         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 133         { .div = 0 }
 134 };
 135
 136 static const struct clksel_rate osc_sys_26m_rates[] = {
 137         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 138         { .div = 0 }
 139 };
 140
 141 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 142         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 143         { .div = 0 }
 144 };
 145
 146 static const struct clksel osc_sys_clksel[] = {
 147         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 148         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 149         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 150         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 151         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 152         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 153         { .parent = NULL },
 154 };
 155
 156 /* Oscillator clock */
 157 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 158 static struct clk osc_sys_ck = {
 159         .name           = "osc_sys_ck",
 160         .ops            = &clkops_null,
 161         .init           = &omap2_init_clksel_parent,
 162         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 163         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 164         .clksel         = osc_sys_clksel,
 165         /* REVISIT: deal with autoextclkmode? */
 166         .flags          = RATE_FIXED,
 167         .recalc         = &omap2_clksel_recalc,
 168 };
 169
 170 static const struct clksel_rate div2_rates[] = {
 171         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 173         { .div = 0 }
 174 };
 175
 176 static const struct clksel sys_clksel[] = {
 177         { .parent = &osc_sys_ck, .rates = div2_rates },
 178         { .parent = NULL }
 179 };
 180
 181 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 182 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 183 static struct clk sys_ck = {
 184         .name           = "sys_ck",
 185         .ops            = &clkops_null,
 186         .parent         = &osc_sys_ck,
 187         .init           = &omap2_init_clksel_parent,
 188         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 189         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 190         .clksel         = sys_clksel,
 191         .recalc         = &omap2_clksel_recalc,
 192 };
 193
 194 static struct clk sys_altclk = {
 195         .name           = "sys_altclk",
 196         .ops            = &clkops_null,
 197 };
 198
 199 /* Optional external clock input for some McBSPs */
 200 static struct clk mcbsp_clks = {
 201         .name           = "mcbsp_clks",
 202         .ops            = &clkops_null,
 203 };
 204
 205 /* PRM EXTERNAL CLOCK OUTPUT */
 206
 207 static struct clk sys_clkout1 = {
 208         .name           = "sys_clkout1",
 209         .ops            = &clkops_omap2_dflt,
 210         .parent         = &osc_sys_ck,
 211         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 212         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 213         .recalc         = &followparent_recalc,
 214 };
 215
 216 /* DPLLS */
 217
 218 /* CM CLOCKS */
 219
 220 static const struct clksel_rate dpll_bypass_rates[] = {
 221         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 222         { .div = 0 }
 223 };
 224
 225 static const struct clksel_rate dpll_locked_rates[] = {
 226         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 227         { .div = 0 }
 228 };
 229
 230 static const struct clksel_rate div16_dpll_rates[] = {
 231         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 233         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 234         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 235         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 236         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 237         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 238         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 239         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 240         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 241         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 242         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 243         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 244         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 245         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 246         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 247         { .div = 0 }
 248 };
 249
 250 /* DPLL1 */
 251 /* MPU clock source */
 252 /* Type: DPLL */
 253 static struct dpll_data dpll1_dd = {
 254         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 255         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 256         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 257         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 258         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 259         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 260         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 261         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 262         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 263         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 264         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 265         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 266         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 267         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 268         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 269         .min_divider    = 1,
 270         .max_divider    = OMAP3_MAX_DPLL_DIV,
 271         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 272 };
 273
 274 static struct clk dpll1_ck = {
 275         .name           = "dpll1_ck",
 276         .ops            = &clkops_null,
 277         .parent         = &sys_ck,
 278         .dpll_data      = &dpll1_dd,
 279         .round_rate     = &omap2_dpll_round_rate,
 280         .set_rate       = &omap3_noncore_dpll_set_rate,
 281         .clkdm_name     = "dpll1_clkdm",
 282         .recalc         = &omap3_dpll_recalc,
 283 };
 284
 285 /*
 286  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 287  * DPLL isn't bypassed.
 288  */
 289 static struct clk dpll1_x2_ck = {
 290         .name           = "dpll1_x2_ck",
 291         .ops            = &clkops_null,
 292         .parent         = &dpll1_ck,
 293         .clkdm_name     = "dpll1_clkdm",
 294         .recalc         = &omap3_clkoutx2_recalc,
 295 };
 296
 297 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 298 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 299         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 300         { .parent = NULL }
 301 };
 302
 303 /*
 304  * Does not exist in the TRM - needed to separate the M2 divider from
 305  * bypass selection in mpu_ck
 306  */
 307 static struct clk dpll1_x2m2_ck = {
 308         .name           = "dpll1_x2m2_ck",
 309         .ops            = &clkops_null,
 310         .parent         = &dpll1_x2_ck,
 311         .init           = &omap2_init_clksel_parent,
 312         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 313         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 314         .clksel         = div16_dpll1_x2m2_clksel,
 315         .clkdm_name     = "dpll1_clkdm",
 316         .recalc         = &omap2_clksel_recalc,
 317 };
 318
 319 /* DPLL2 */
 320 /* IVA2 clock source */
 321 /* Type: DPLL */
 322
 323 static struct dpll_data dpll2_dd = {
 324         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 325         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 326         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 327         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 328         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 329         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 330         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 331                                 (1 << DPLL_LOW_POWER_BYPASS),
 332         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 333         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 334         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 335         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 336         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 337         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 338         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 339         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 340         .min_divider    = 1,
 341         .max_divider    = OMAP3_MAX_DPLL_DIV,
 342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 343 };
 344
 345 static struct clk dpll2_ck = {
 346         .name           = "dpll2_ck",
 347         .ops            = &clkops_noncore_dpll_ops,
 348         .parent         = &sys_ck,
 349         .dpll_data      = &dpll2_dd,
 350         .round_rate     = &omap2_dpll_round_rate,
 351         .set_rate       = &omap3_noncore_dpll_set_rate,
 352         .clkdm_name     = "dpll2_clkdm",
 353         .recalc         = &omap3_dpll_recalc,
 354 };
 355
 356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 358         { .parent = NULL }
 359 };
 360
 361 /*
 362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 363  * or CLKOUTX2. CLKOUT seems most plausible.
 364  */
 365 static struct clk dpll2_m2_ck = {
 366         .name           = "dpll2_m2_ck",
 367         .ops            = &clkops_null,
 368         .parent         = &dpll2_ck,
 369         .init           = &omap2_init_clksel_parent,
 370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 371                                           OMAP3430_CM_CLKSEL2_PLL),
 372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 373         .clksel         = div16_dpll2_m2x2_clksel,
 374         .clkdm_name     = "dpll2_clkdm",
 375         .recalc         = &omap2_clksel_recalc,
 376 };
 377
 378 /*
 379  * DPLL3
 380  * Source clock for all interfaces and for some device fclks
 381  * REVISIT: Also supports fast relock bypass - not included below
 382  */
 383 static struct dpll_data dpll3_dd = {
 384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 387         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 388         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 389         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 390         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 391         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 392         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 393         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 394         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 395         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 396         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 397         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 398         .min_divider    = 1,
 399         .max_divider    = OMAP3_MAX_DPLL_DIV,
 400         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 401 };
 402
 403 static struct clk dpll3_ck = {
 404         .name           = "dpll3_ck",
 405         .ops            = &clkops_null,
 406         .parent         = &sys_ck,
 407         .dpll_data      = &dpll3_dd,
 408         .round_rate     = &omap2_dpll_round_rate,
 409         .clkdm_name     = "dpll3_clkdm",
 410         .recalc         = &omap3_dpll_recalc,
 411 };
 412
 413 /*
 414  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 415  * DPLL isn't bypassed
 416  */
 417 static struct clk dpll3_x2_ck = {
 418         .name           = "dpll3_x2_ck",
 419         .ops            = &clkops_null,
 420         .parent         = &dpll3_ck,
 421         .clkdm_name     = "dpll3_clkdm",
 422         .recalc         = &omap3_clkoutx2_recalc,
 423 };
 424
 425 static const struct clksel_rate div31_dpll3_rates[] = {
 426         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 427         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 428         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 429         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 430         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 431         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 432         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 433         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 434         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 435         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 436         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 437         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 438         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 439         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 440         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 441         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 442         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 443         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 444         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 445         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 446         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 447         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 448         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 449         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 450         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 451         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 452         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 453         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 454         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 455         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 456         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 457         { .div = 0 },
 458 };
 459
 460 static const struct clksel div31_dpll3m2_clksel[] = {
 461         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 462         { .parent = NULL }
 463 };
 464
 465 /* DPLL3 output M2 - primary control point for CORE speed */
 466 static struct clk dpll3_m2_ck = {
 467         .name           = "dpll3_m2_ck",
 468         .ops            = &clkops_null,
 469         .parent         = &dpll3_ck,
 470         .init           = &omap2_init_clksel_parent,
 471         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 472         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 473         .clksel         = div31_dpll3m2_clksel,
 474         .clkdm_name     = "dpll3_clkdm",
 475         .round_rate     = &omap2_clksel_round_rate,
 476         .set_rate       = &omap3_core_dpll_m2_set_rate,
 477         .recalc         = &omap2_clksel_recalc,
 478 };
 479
 480 static const struct clksel core_ck_clksel[] = {
 481         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 482         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 483         { .parent = NULL }
 484 };
 485
 486 static struct clk core_ck = {
 487         .name           = "core_ck",
 488         .ops            = &clkops_null,
 489         .init           = &omap2_init_clksel_parent,
 490         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 491         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 492         .clksel         = core_ck_clksel,
 493         .recalc         = &omap2_clksel_recalc,
 494 };
 495
 496 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 497         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 498         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 499         { .parent = NULL }
 500 };
 501
 502 static struct clk dpll3_m2x2_ck = {
 503         .name           = "dpll3_m2x2_ck",
 504         .ops            = &clkops_null,
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 508         .clksel         = dpll3_m2x2_ck_clksel,
 509         .clkdm_name     = "dpll3_clkdm",
 510         .recalc         = &omap2_clksel_recalc,
 511 };
 512
 513 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 514 static const struct clksel div16_dpll3_clksel[] = {
 515         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 516         { .parent = NULL }
 517 };
 518
 519 /* This virtual clock is the source for dpll3_m3x2_ck */
 520 static struct clk dpll3_m3_ck = {
 521         .name           = "dpll3_m3_ck",
 522         .ops            = &clkops_null,
 523         .parent         = &dpll3_ck,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 527         .clksel         = div16_dpll3_clksel,
 528         .clkdm_name     = "dpll3_clkdm",
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 533 static struct clk dpll3_m3x2_ck = {
 534         .name           = "dpll3_m3x2_ck",
 535         .ops            = &clkops_omap2_dflt_wait,
 536         .parent         = &dpll3_m3_ck,
 537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 539         .flags          = INVERT_ENABLE,
 540         .clkdm_name     = "dpll3_clkdm",
 541         .recalc         = &omap3_clkoutx2_recalc,
 542 };
 543
 544 static const struct clksel emu_core_alwon_ck_clksel[] = {
 545         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 546         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 547         { .parent = NULL }
 548 };
 549
 550 static struct clk emu_core_alwon_ck = {
 551         .name           = "emu_core_alwon_ck",
 552         .ops            = &clkops_null,
 553         .parent         = &dpll3_m3x2_ck,
 554         .init           = &omap2_init_clksel_parent,
 555         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 556         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 557         .clksel         = emu_core_alwon_ck_clksel,
 558         .clkdm_name     = "dpll3_clkdm",
 559         .recalc         = &omap2_clksel_recalc,
 560 };
 561
 562 /* DPLL4 */
 563 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 564 /* Type: DPLL */
 565 static struct dpll_data dpll4_dd = {
 566         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 567         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 568         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 569         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 570         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 571         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 572         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 573         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 574         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 575         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 576         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 577         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 578         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 579         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 580         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 581         .min_divider    = 1,
 582         .max_divider    = OMAP3_MAX_DPLL_DIV,
 583         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 584 };
 585
 586 static struct clk dpll4_ck = {
 587         .name           = "dpll4_ck",
 588         .ops            = &clkops_noncore_dpll_ops,
 589         .parent         = &sys_ck,
 590         .dpll_data      = &dpll4_dd,
 591         .round_rate     = &omap2_dpll_round_rate,
 592         .set_rate       = &omap3_dpll4_set_rate,
 593         .clkdm_name     = "dpll4_clkdm",
 594         .recalc         = &omap3_dpll_recalc,
 595 };
 596
 597 /*
 598  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 599  * DPLL isn't bypassed --
 600  * XXX does this serve any downstream clocks?
 601  */
 602 static struct clk dpll4_x2_ck = {
 603         .name           = "dpll4_x2_ck",
 604         .ops            = &clkops_null,
 605         .parent         = &dpll4_ck,
 606         .clkdm_name     = "dpll4_clkdm",
 607         .recalc         = &omap3_clkoutx2_recalc,
 608 };
 609
 610 static const struct clksel div16_dpll4_clksel[] = {
 611         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 612         { .parent = NULL }
 613 };
 614
 615 /* This virtual clock is the source for dpll4_m2x2_ck */
 616 static struct clk dpll4_m2_ck = {
 617         .name           = "dpll4_m2_ck",
 618         .ops            = &clkops_null,
 619         .parent         = &dpll4_ck,
 620         .init           = &omap2_init_clksel_parent,
 621         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 622         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 623         .clksel         = div16_dpll4_clksel,
 624         .clkdm_name     = "dpll4_clkdm",
 625         .recalc         = &omap2_clksel_recalc,
 626 };
 627
 628 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 629 static struct clk dpll4_m2x2_ck = {
 630         .name           = "dpll4_m2x2_ck",
 631         .ops            = &clkops_omap2_dflt_wait,
 632         .parent         = &dpll4_m2_ck,
 633         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 634         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 635         .flags          = INVERT_ENABLE,
 636         .clkdm_name     = "dpll4_clkdm",
 637         .recalc         = &omap3_clkoutx2_recalc,
 638 };
 639
 640 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 641         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 642         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 643         { .parent = NULL }
 644 };
 645
 646 /*
 647  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 648  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 649  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 650  * CM_96K_(F)CLK.
 651  */
 652 static struct clk omap_96m_alwon_fck = {
 653         .name           = "omap_96m_alwon_fck",
 654         .ops            = &clkops_null,
 655         .parent         = &dpll4_m2x2_ck,
 656         .init           = &omap2_init_clksel_parent,
 657         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 658         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 659         .clksel         = omap_96m_alwon_fck_clksel,
 660         .recalc         = &omap2_clksel_recalc,
 661 };
 662
 663 static struct clk cm_96m_fck = {
 664         .name           = "cm_96m_fck",
 665         .ops            = &clkops_null,
 666         .parent         = &omap_96m_alwon_fck,
 667         .recalc         = &followparent_recalc,
 668 };
 669
 670 static const struct clksel_rate omap_96m_dpll_rates[] = {
 671         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 672         { .div = 0 }
 673 };
 674
 675 static const struct clksel_rate omap_96m_sys_rates[] = {
 676         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 677         { .div = 0 }
 678 };
 679
 680 static const struct clksel omap_96m_fck_clksel[] = {
 681         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 682         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 683         { .parent = NULL }
 684 };
 685
 686 static struct clk omap_96m_fck = {
 687         .name           = "omap_96m_fck",
 688         .ops            = &clkops_null,
 689         .parent         = &sys_ck,
 690         .init           = &omap2_init_clksel_parent,
 691         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 692         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 693         .clksel         = omap_96m_fck_clksel,
 694         .recalc         = &omap2_clksel_recalc,
 695 };
 696
 697 /* This virtual clock is the source for dpll4_m3x2_ck */
 698 static struct clk dpll4_m3_ck = {
 699         .name           = "dpll4_m3_ck",
 700         .ops            = &clkops_null,
 701         .parent         = &dpll4_ck,
 702         .init           = &omap2_init_clksel_parent,
 703         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 704         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 705         .clksel         = div16_dpll4_clksel,
 706         .clkdm_name     = "dpll4_clkdm",
 707         .recalc         = &omap2_clksel_recalc,
 708 };
 709
 710 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 711 static struct clk dpll4_m3x2_ck = {
 712         .name           = "dpll4_m3x2_ck",
 713         .ops            = &clkops_omap2_dflt_wait,
 714         .parent         = &dpll4_m3_ck,
 715         .init           = &omap2_init_clksel_parent,
 716         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 717         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 718         .flags          = INVERT_ENABLE,
 719         .clkdm_name     = "dpll4_clkdm",
 720         .recalc         = &omap3_clkoutx2_recalc,
 721 };
 722
 723 static const struct clksel virt_omap_54m_fck_clksel[] = {
 724         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 725         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 726         { .parent = NULL }
 727 };
 728
 729 static struct clk virt_omap_54m_fck = {
 730         .name           = "virt_omap_54m_fck",
 731         .ops            = &clkops_null,
 732         .parent         = &dpll4_m3x2_ck,
 733         .init           = &omap2_init_clksel_parent,
 734         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 735         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 736         .clksel         = virt_omap_54m_fck_clksel,
 737         .recalc         = &omap2_clksel_recalc,
 738 };
 739
 740 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 741         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 742         { .div = 0 }
 743 };
 744
 745 static const struct clksel_rate omap_54m_alt_rates[] = {
 746         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 747         { .div = 0 }
 748 };
 749
 750 static const struct clksel omap_54m_clksel[] = {
 751         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 752         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 753         { .parent = NULL }
 754 };
 755
 756 static struct clk omap_54m_fck = {
 757         .name           = "omap_54m_fck",
 758         .ops            = &clkops_null,
 759         .init           = &omap2_init_clksel_parent,
 760         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 761         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 762         .clksel         = omap_54m_clksel,
 763         .recalc         = &omap2_clksel_recalc,
 764 };
 765
 766 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 767         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 768         { .div = 0 }
 769 };
 770
 771 static const struct clksel_rate omap_48m_alt_rates[] = {
 772         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 773         { .div = 0 }
 774 };
 775
 776 static const struct clksel omap_48m_clksel[] = {
 777         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 778         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 779         { .parent = NULL }
 780 };
 781
 782 static struct clk omap_48m_fck = {
 783         .name           = "omap_48m_fck",
 784         .ops            = &clkops_null,
 785         .init           = &omap2_init_clksel_parent,
 786         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 787         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 788         .clksel         = omap_48m_clksel,
 789         .recalc         = &omap2_clksel_recalc,
 790 };
 791
 792 static struct clk omap_12m_fck = {
 793         .name           = "omap_12m_fck",
 794         .ops            = &clkops_null,
 795         .parent         = &omap_48m_fck,
 796         .fixed_div      = 4,
 797         .recalc         = &omap2_fixed_divisor_recalc,
 798 };
 799
 800 /* This virstual clock is the source for dpll4_m4x2_ck */
 801 static struct clk dpll4_m4_ck = {
 802         .name           = "dpll4_m4_ck",
 803         .ops            = &clkops_null,
 804         .parent         = &dpll4_ck,
 805         .init           = &omap2_init_clksel_parent,
 806         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 807         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 808         .clksel         = div16_dpll4_clksel,
 809         .clkdm_name     = "dpll4_clkdm",
 810         .recalc         = &omap2_clksel_recalc,
 811         .set_rate       = &omap2_clksel_set_rate,
 812         .round_rate     = &omap2_clksel_round_rate,
 813 };
 814
 815 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 816 static struct clk dpll4_m4x2_ck = {
 817         .name           = "dpll4_m4x2_ck",
 818         .ops            = &clkops_omap2_dflt_wait,
 819         .parent         = &dpll4_m4_ck,
 820         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 821         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 822         .flags          = INVERT_ENABLE,
 823         .clkdm_name     = "dpll4_clkdm",
 824         .recalc         = &omap3_clkoutx2_recalc,
 825 };
 826
 827 /* This virtual clock is the source for dpll4_m5x2_ck */
 828 static struct clk dpll4_m5_ck = {
 829         .name           = "dpll4_m5_ck",
 830         .ops            = &clkops_null,
 831         .parent         = &dpll4_ck,
 832         .init           = &omap2_init_clksel_parent,
 833         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 834         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 835         .clksel         = div16_dpll4_clksel,
 836         .clkdm_name     = "dpll4_clkdm",
 837         .recalc         = &omap2_clksel_recalc,
 838 };
 839
 840 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 841 static struct clk dpll4_m5x2_ck = {
 842         .name           = "dpll4_m5x2_ck",
 843         .ops            = &clkops_omap2_dflt_wait,
 844         .parent         = &dpll4_m5_ck,
 845         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 846         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 847         .flags          = INVERT_ENABLE,
 848         .clkdm_name     = "dpll4_clkdm",
 849         .recalc         = &omap3_clkoutx2_recalc,
 850 };
 851
 852 /* This virtual clock is the source for dpll4_m6x2_ck */
 853 static struct clk dpll4_m6_ck = {
 854         .name           = "dpll4_m6_ck",
 855         .ops            = &clkops_null,
 856         .parent         = &dpll4_ck,
 857         .init           = &omap2_init_clksel_parent,
 858         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 859         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 860         .clksel         = div16_dpll4_clksel,
 861         .clkdm_name     = "dpll4_clkdm",
 862         .recalc         = &omap2_clksel_recalc,
 863 };
 864
 865 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 866 static struct clk dpll4_m6x2_ck = {
 867         .name           = "dpll4_m6x2_ck",
 868         .ops            = &clkops_omap2_dflt_wait,
 869         .parent         = &dpll4_m6_ck,
 870         .init           = &omap2_init_clksel_parent,
 871         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 872         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 873         .flags          = INVERT_ENABLE,
 874         .clkdm_name     = "dpll4_clkdm",
 875         .recalc         = &omap3_clkoutx2_recalc,
 876 };
 877
 878 static struct clk emu_per_alwon_ck = {
 879         .name           = "emu_per_alwon_ck",
 880         .ops            = &clkops_null,
 881         .parent         = &dpll4_m6x2_ck,
 882         .clkdm_name     = "dpll4_clkdm",
 883         .recalc         = &followparent_recalc,
 884 };
 885
 886 /* DPLL5 */
 887 /* Supplies 120MHz clock, USIM source clock */
 888 /* Type: DPLL */
 889 /* 3430ES2 only */
 890 static struct dpll_data dpll5_dd = {
 891         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 892         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 893         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 894         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 895         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 896         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 897         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 898         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 899         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 900         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 901         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 902         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 903         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 904         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 905         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 906         .min_divider    = 1,
 907         .max_divider    = OMAP3_MAX_DPLL_DIV,
 908         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 909 };
 910
 911 static struct clk dpll5_ck = {
 912         .name           = "dpll5_ck",
 913         .ops            = &clkops_noncore_dpll_ops,
 914         .parent         = &sys_ck,
 915         .dpll_data      = &dpll5_dd,
 916         .round_rate     = &omap2_dpll_round_rate,
 917         .set_rate       = &omap3_noncore_dpll_set_rate,
 918         .clkdm_name     = "dpll5_clkdm",
 919         .recalc         = &omap3_dpll_recalc,
 920 };
 921
 922 static const struct clksel div16_dpll5_clksel[] = {
 923         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 924         { .parent = NULL }
 925 };
 926
 927 static struct clk dpll5_m2_ck = {
 928         .name           = "dpll5_m2_ck",
 929         .ops            = &clkops_null,
 930         .parent         = &dpll5_ck,
 931         .init           = &omap2_init_clksel_parent,
 932         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 933         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 934         .clksel         = div16_dpll5_clksel,
 935         .clkdm_name     = "dpll5_clkdm",
 936         .recalc         = &omap2_clksel_recalc,
 937 };
 938
 939 static const struct clksel omap_120m_fck_clksel[] = {
 940         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 941         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 942         { .parent = NULL }
 943 };
 944
 945 static struct clk omap_120m_fck = {
 946         .name           = "omap_120m_fck",
 947         .ops            = &clkops_null,
 948         .parent         = &dpll5_m2_ck,
 949         .init           = &omap2_init_clksel_parent,
 950         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 951         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 952         .clksel         = omap_120m_fck_clksel,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 /* CM EXTERNAL CLOCK OUTPUTS */
 957
 958 static const struct clksel_rate clkout2_src_core_rates[] = {
 959         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 960         { .div = 0 }
 961 };
 962
 963 static const struct clksel_rate clkout2_src_sys_rates[] = {
 964         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 965         { .div = 0 }
 966 };
 967
 968 static const struct clksel_rate clkout2_src_96m_rates[] = {
 969         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 970         { .div = 0 }
 971 };
 972
 973 static const struct clksel_rate clkout2_src_54m_rates[] = {
 974         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 975         { .div = 0 }
 976 };
 977
 978 static const struct clksel clkout2_src_clksel[] = {
 979         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 980         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 981         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 982         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 983         { .parent = NULL }
 984 };
 985
 986 static struct clk clkout2_src_ck = {
 987         .name           = "clkout2_src_ck",
 988         .ops            = &clkops_omap2_dflt,
 989         .init           = &omap2_init_clksel_parent,
 990         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 991         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 992         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 993         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 994         .clksel         = clkout2_src_clksel,
 995         .clkdm_name     = "core_clkdm",
 996         .recalc         = &omap2_clksel_recalc,
 997 };
 998
 999 static const struct clksel_rate sys_clkout2_rates[] = {
1000         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1001         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1002         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1003         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1004         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1005         { .div = 0 },
1006 };
1007
1008 static const struct clksel sys_clkout2_clksel[] = {
1009         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1010         { .parent = NULL },
1011 };
1012
1013 static struct clk sys_clkout2 = {
1014         .name           = "sys_clkout2",
1015         .ops            = &clkops_null,
1016         .init           = &omap2_init_clksel_parent,
1017         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1018         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1019         .clksel         = sys_clkout2_clksel,
1020         .recalc         = &omap2_clksel_recalc,
1021 };
1022
1023 /* CM OUTPUT CLOCKS */
1024
1025 static struct clk corex2_fck = {
1026         .name           = "corex2_fck",
1027         .ops            = &clkops_null,
1028         .parent         = &dpll3_m2x2_ck,
1029         .recalc         = &followparent_recalc,
1030 };
1031
1032 /* DPLL power domain clock controls */
1033
1034 static const struct clksel_rate div4_rates[] = {
1035         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1036         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1037         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1038         { .div = 0 }
1039 };
1040
1041 static const struct clksel div4_core_clksel[] = {
1042         { .parent = &core_ck, .rates = div4_rates },
1043         { .parent = NULL }
1044 };
1045
1046 /*
1047  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1048  * may be inconsistent here?
1049  */
1050 static struct clk dpll1_fck = {
1051         .name           = "dpll1_fck",
1052         .ops            = &clkops_null,
1053         .parent         = &core_ck,
1054         .init           = &omap2_init_clksel_parent,
1055         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1056         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1057         .clksel         = div4_core_clksel,
1058         .recalc         = &omap2_clksel_recalc,
1059 };
1060
1061 /*
1062  * MPU clksel:
1063  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1064  * derives from the high-frequency bypass clock originating from DPLL3,
1065  * called 'dpll1_fck'
1066  */
1067 static const struct clksel mpu_clksel[] = {
1068         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1069         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1070         { .parent = NULL }
1071 };
1072
1073 static struct clk mpu_ck = {
1074         .name           = "mpu_ck",
1075         .ops            = &clkops_null,
1076         .parent         = &dpll1_x2m2_ck,
1077         .init           = &omap2_init_clksel_parent,
1078         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1079         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1080         .clksel         = mpu_clksel,
1081         .clkdm_name     = "mpu_clkdm",
1082         .recalc         = &omap2_clksel_recalc,
1083 };
1084
1085 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1086 static const struct clksel_rate arm_fck_rates[] = {
1087         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1088         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1089         { .div = 0 },
1090 };
1091
1092 static const struct clksel arm_fck_clksel[] = {
1093         { .parent = &mpu_ck, .rates = arm_fck_rates },
1094         { .parent = NULL }
1095 };
1096
1097 static struct clk arm_fck = {
1098         .name           = "arm_fck",
1099         .ops            = &clkops_null,
1100         .parent         = &mpu_ck,
1101         .init           = &omap2_init_clksel_parent,
1102         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1103         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1104         .clksel         = arm_fck_clksel,
1105         .recalc         = &omap2_clksel_recalc,
1106 };
1107
1108 /* XXX What about neon_clkdm ? */
1109
1110 /*
1111  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1112  * although it is referenced - so this is a guess
1113  */
1114 static struct clk emu_mpu_alwon_ck = {
1115         .name           = "emu_mpu_alwon_ck",
1116         .ops            = &clkops_null,
1117         .parent         = &mpu_ck,
1118         .recalc         = &followparent_recalc,
1119 };
1120
1121 static struct clk dpll2_fck = {
1122         .name           = "dpll2_fck",
1123         .ops            = &clkops_null,
1124         .parent         = &core_ck,
1125         .init           = &omap2_init_clksel_parent,
1126         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1127         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1128         .clksel         = div4_core_clksel,
1129         .recalc         = &omap2_clksel_recalc,
1130 };
1131
1132 /*
1133  * IVA2 clksel:
1134  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1135  * derives from the high-frequency bypass clock originating from DPLL3,
1136  * called 'dpll2_fck'
1137  */
1138
1139 static const struct clksel iva2_clksel[] = {
1140         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1141         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1142         { .parent = NULL }
1143 };
1144
1145 static struct clk iva2_ck = {
1146         .name           = "iva2_ck",
1147         .ops            = &clkops_omap2_dflt_wait,
1148         .parent         = &dpll2_m2_ck,
1149         .init           = &omap2_init_clksel_parent,
1150         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1151         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1152         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1153                                           OMAP3430_CM_IDLEST_PLL),
1154         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1155         .clksel         = iva2_clksel,
1156         .clkdm_name     = "iva2_clkdm",
1157         .recalc         = &omap2_clksel_recalc,
1158 };
1159
1160 /* Common interface clocks */
1161
1162 static const struct clksel div2_core_clksel[] = {
1163         { .parent = &core_ck, .rates = div2_rates },
1164         { .parent = NULL }
1165 };
1166
1167 static struct clk l3_ick = {
1168         .name           = "l3_ick",
1169         .ops            = &clkops_null,
1170         .parent         = &core_ck,
1171         .init           = &omap2_init_clksel_parent,
1172         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1173         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1174         .clksel         = div2_core_clksel,
1175         .clkdm_name     = "core_l3_clkdm",
1176         .recalc         = &omap2_clksel_recalc,
1177 };
1178
1179 static const struct clksel div2_l3_clksel[] = {
1180         { .parent = &l3_ick, .rates = div2_rates },
1181         { .parent = NULL }
1182 };
1183
1184 static struct clk l4_ick = {
1185         .name           = "l4_ick",
1186         .ops            = &clkops_null,
1187         .parent         = &l3_ick,
1188         .init           = &omap2_init_clksel_parent,
1189         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1190         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1191         .clksel         = div2_l3_clksel,
1192         .clkdm_name     = "core_l4_clkdm",
1193         .recalc         = &omap2_clksel_recalc,
1194
1195 };
1196
1197 static const struct clksel div2_l4_clksel[] = {
1198         { .parent = &l4_ick, .rates = div2_rates },
1199         { .parent = NULL }
1200 };
1201
1202 static struct clk rm_ick = {
1203         .name           = "rm_ick",
1204         .ops            = &clkops_null,
1205         .parent         = &l4_ick,
1206         .init           = &omap2_init_clksel_parent,
1207         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1208         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1209         .clksel         = div2_l4_clksel,
1210         .recalc         = &omap2_clksel_recalc,
1211 };
1212
1213 /* GFX power domain */
1214
1215 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1216
1217 static const struct clksel gfx_l3_clksel[] = {
1218         { .parent = &l3_ick, .rates = gfx_l3_rates },
1219         { .parent = NULL }
1220 };
1221
1222 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1223 static struct clk gfx_l3_ck = {
1224         .name           = "gfx_l3_ck",
1225         .ops            = &clkops_omap2_dflt_wait,
1226         .parent         = &l3_ick,
1227         .init           = &omap2_init_clksel_parent,
1228         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1229         .enable_bit     = OMAP_EN_GFX_SHIFT,
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static struct clk gfx_l3_fck = {
1234         .name           = "gfx_l3_fck",
1235         .ops            = &clkops_null,
1236         .parent         = &gfx_l3_ck,
1237         .init           = &omap2_init_clksel_parent,
1238         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1239         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1240         .clksel         = gfx_l3_clksel,
1241         .clkdm_name     = "gfx_3430es1_clkdm",
1242         .recalc         = &omap2_clksel_recalc,
1243 };
1244
1245 static struct clk gfx_l3_ick = {
1246         .name           = "gfx_l3_ick",
1247         .ops            = &clkops_null,
1248         .parent         = &gfx_l3_ck,
1249         .clkdm_name     = "gfx_3430es1_clkdm",
1250         .recalc         = &followparent_recalc,
1251 };
1252
1253 static struct clk gfx_cg1_ck = {
1254         .name           = "gfx_cg1_ck",
1255         .ops            = &clkops_omap2_dflt_wait,
1256         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1257         .init           = &omap2_init_clk_clkdm,
1258         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1259         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1260         .clkdm_name     = "gfx_3430es1_clkdm",
1261         .recalc         = &followparent_recalc,
1262 };
1263
1264 static struct clk gfx_cg2_ck = {
1265         .name           = "gfx_cg2_ck",
1266         .ops            = &clkops_omap2_dflt_wait,
1267         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1268         .init           = &omap2_init_clk_clkdm,
1269         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1270         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1271         .clkdm_name     = "gfx_3430es1_clkdm",
1272         .recalc         = &followparent_recalc,
1273 };
1274
1275 /* SGX power domain - 3430ES2 only */
1276
1277 static const struct clksel_rate sgx_core_rates[] = {
1278         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1279         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1280         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1281         { .div = 0 },
1282 };
1283
1284 static const struct clksel_rate sgx_96m_rates[] = {
1285         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1286         { .div = 0 },
1287 };
1288
1289 static const struct clksel sgx_clksel[] = {
1290         { .parent = &core_ck,    .rates = sgx_core_rates },
1291         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1292         { .parent = NULL },
1293 };
1294
1295 static struct clk sgx_fck = {
1296         .name           = "sgx_fck",
1297         .ops            = &clkops_omap2_dflt_wait,
1298         .init           = &omap2_init_clksel_parent,
1299         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1300         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1301         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1302         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1303         .clksel         = sgx_clksel,
1304         .clkdm_name     = "sgx_clkdm",
1305         .recalc         = &omap2_clksel_recalc,
1306 };
1307
1308 static struct clk sgx_ick = {
1309         .name           = "sgx_ick",
1310         .ops            = &clkops_omap2_dflt_wait,
1311         .parent         = &l3_ick,
1312         .init           = &omap2_init_clk_clkdm,
1313         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1314         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1315         .clkdm_name     = "sgx_clkdm",
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 /* CORE power domain */
1320
1321 static struct clk d2d_26m_fck = {
1322         .name           = "d2d_26m_fck",
1323         .ops            = &clkops_omap2_dflt_wait,
1324         .parent         = &sys_ck,
1325         .init           = &omap2_init_clk_clkdm,
1326         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1327         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1328         .clkdm_name     = "d2d_clkdm",
1329         .recalc         = &followparent_recalc,
1330 };
1331
1332 static const struct clksel omap343x_gpt_clksel[] = {
1333         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1334         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1335         { .parent = NULL}
1336 };
1337
1338 static struct clk gpt10_fck = {
1339         .name           = "gpt10_fck",
1340         .ops            = &clkops_omap2_dflt_wait,
1341         .parent         = &sys_ck,
1342         .init           = &omap2_init_clksel_parent,
1343         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1344         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1345         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1346         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1347         .clksel         = omap343x_gpt_clksel,
1348         .clkdm_name     = "core_l4_clkdm",
1349         .recalc         = &omap2_clksel_recalc,
1350 };
1351
1352 static struct clk gpt11_fck = {
1353         .name           = "gpt11_fck",
1354         .ops            = &clkops_omap2_dflt_wait,
1355         .parent         = &sys_ck,
1356         .init           = &omap2_init_clksel_parent,
1357         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1358         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1359         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1360         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1361         .clksel         = omap343x_gpt_clksel,
1362         .clkdm_name     = "core_l4_clkdm",
1363         .recalc         = &omap2_clksel_recalc,
1364 };
1365
1366 static struct clk cpefuse_fck = {
1367         .name           = "cpefuse_fck",
1368         .ops            = &clkops_omap2_dflt,
1369         .parent         = &sys_ck,
1370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1371         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1372         .recalc         = &followparent_recalc,
1373 };
1374
1375 static struct clk ts_fck = {
1376         .name           = "ts_fck",
1377         .ops            = &clkops_omap2_dflt,
1378         .parent         = &omap_32k_fck,
1379         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1380         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1381         .recalc         = &followparent_recalc,
1382 };
1383
1384 static struct clk usbtll_fck = {
1385         .name           = "usbtll_fck",
1386         .ops            = &clkops_omap2_dflt,
1387         .parent         = &omap_120m_fck,
1388         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1389         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1390         .recalc         = &followparent_recalc,
1391 };
1392
1393 /* CORE 96M FCLK-derived clocks */
1394
1395 static struct clk core_96m_fck = {
1396         .name           = "core_96m_fck",
1397         .ops            = &clkops_null,
1398         .parent         = &omap_96m_fck,
1399         .clkdm_name     = "core_l4_clkdm",
1400         .recalc         = &followparent_recalc,
1401 };
1402
1403 static struct clk mmchs3_fck = {
1404         .name           = "mmchs_fck",
1405         .ops            = &clkops_omap2_dflt_wait,
1406         .id             = 2,
1407         .parent         = &core_96m_fck,
1408         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1409         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1410         .clkdm_name     = "core_l4_clkdm",
1411         .recalc         = &followparent_recalc,
1412 };
1413
1414 static struct clk mmchs2_fck = {
1415         .name           = "mmchs_fck",
1416         .ops            = &clkops_omap2_dflt_wait,
1417         .id             = 1,
1418         .parent         = &core_96m_fck,
1419         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1420         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1421         .clkdm_name     = "core_l4_clkdm",
1422         .recalc         = &followparent_recalc,
1423 };
1424
1425 static struct clk mspro_fck = {
1426         .name           = "mspro_fck",
1427         .ops            = &clkops_omap2_dflt_wait,
1428         .parent         = &core_96m_fck,
1429         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1430         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1431         .clkdm_name     = "core_l4_clkdm",
1432         .recalc         = &followparent_recalc,
1433 };
1434
1435 static struct clk mmchs1_fck = {
1436         .name           = "mmchs_fck",
1437         .ops            = &clkops_omap2_dflt_wait,
1438         .parent         = &core_96m_fck,
1439         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1440         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1441         .clkdm_name     = "core_l4_clkdm",
1442         .recalc         = &followparent_recalc,
1443 };
1444
1445 static struct clk i2c3_fck = {
1446         .name           = "i2c_fck",
1447         .ops            = &clkops_omap2_dflt_wait,
1448         .id             = 3,
1449         .parent         = &core_96m_fck,
1450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1452         .clkdm_name     = "core_l4_clkdm",
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk i2c2_fck = {
1457         .name           = "i2c_fck",
1458         .ops            = &clkops_omap2_dflt_wait,
1459         .id             = 2,
1460         .parent         = &core_96m_fck,
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1463         .clkdm_name     = "core_l4_clkdm",
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk i2c1_fck = {
1468         .name           = "i2c_fck",
1469         .ops            = &clkops_omap2_dflt_wait,
1470         .id             = 1,
1471         .parent         = &core_96m_fck,
1472         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1474         .clkdm_name     = "core_l4_clkdm",
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 /*
1479  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1480  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1481  */
1482 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1483         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1484         { .div = 0 }
1485 };
1486
1487 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1488         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1489         { .div = 0 }
1490 };
1491
1492 static const struct clksel mcbsp_15_clksel[] = {
1493         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1494         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1495         { .parent = NULL }
1496 };
1497
1498 static struct clk mcbsp5_fck = {
1499         .name           = "mcbsp_fck",
1500         .ops            = &clkops_omap2_dflt_wait,
1501         .id             = 5,
1502         .init           = &omap2_init_clksel_parent,
1503         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1505         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1506         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1507         .clksel         = mcbsp_15_clksel,
1508         .clkdm_name     = "core_l4_clkdm",
1509         .recalc         = &omap2_clksel_recalc,
1510 };
1511
1512 static struct clk mcbsp1_fck = {
1513         .name           = "mcbsp_fck",
1514         .ops            = &clkops_omap2_dflt_wait,
1515         .id             = 1,
1516         .init           = &omap2_init_clksel_parent,
1517         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1518         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1519         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1520         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1521         .clksel         = mcbsp_15_clksel,
1522         .clkdm_name     = "core_l4_clkdm",
1523         .recalc         = &omap2_clksel_recalc,
1524 };
1525
1526 /* CORE_48M_FCK-derived clocks */
1527
1528 static struct clk core_48m_fck = {
1529         .name           = "core_48m_fck",
1530         .ops            = &clkops_null,
1531         .parent         = &omap_48m_fck,
1532         .clkdm_name     = "core_l4_clkdm",
1533         .recalc         = &followparent_recalc,
1534 };
1535
1536 static struct clk mcspi4_fck = {
1537         .name           = "mcspi_fck",
1538         .ops            = &clkops_omap2_dflt_wait,
1539         .id             = 4,
1540         .parent         = &core_48m_fck,
1541         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1542         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1543         .recalc         = &followparent_recalc,
1544 };
1545
1546 static struct clk mcspi3_fck = {
1547         .name           = "mcspi_fck",
1548         .ops            = &clkops_omap2_dflt_wait,
1549         .id             = 3,
1550         .parent         = &core_48m_fck,
1551         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk mcspi2_fck = {
1557         .name           = "mcspi_fck",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .id             = 2,
1560         .parent         = &core_48m_fck,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk mcspi1_fck = {
1567         .name           = "mcspi_fck",
1568         .ops            = &clkops_omap2_dflt_wait,
1569         .id             = 1,
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk uart2_fck = {
1577         .name           = "uart2_fck",
1578         .ops            = &clkops_omap2_dflt_wait,
1579         .parent         = &core_48m_fck,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk uart1_fck = {
1586         .name           = "uart1_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &core_48m_fck,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 static struct clk fshostusb_fck = {
1595         .name           = "fshostusb_fck",
1596         .ops            = &clkops_omap2_dflt_wait,
1597         .parent         = &core_48m_fck,
1598         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 /* CORE_12M_FCK based clocks */
1604
1605 static struct clk core_12m_fck = {
1606         .name           = "core_12m_fck",
1607         .ops            = &clkops_null,
1608         .parent         = &omap_12m_fck,
1609         .clkdm_name     = "core_l4_clkdm",
1610         .recalc         = &followparent_recalc,
1611 };
1612
1613 static struct clk hdq_fck = {
1614         .name           = "hdq_fck",
1615         .ops            = &clkops_omap2_dflt_wait,
1616         .parent         = &core_12m_fck,
1617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1618         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1619         .recalc         = &followparent_recalc,
1620 };
1621
1622 /* DPLL3-derived clock */
1623
1624 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1625         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1626         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1627         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1628         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1629         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1630         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1631         { .div = 0 }
1632 };
1633
1634 static const struct clksel ssi_ssr_clksel[] = {
1635         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1636         { .parent = NULL }
1637 };
1638
1639 static struct clk ssi_ssr_fck = {
1640         .name           = "ssi_ssr_fck",
1641         .ops            = &clkops_omap2_dflt,
1642         .init           = &omap2_init_clksel_parent,
1643         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1645         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1646         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1647         .clksel         = ssi_ssr_clksel,
1648         .clkdm_name     = "core_l4_clkdm",
1649         .recalc         = &omap2_clksel_recalc,
1650 };
1651
1652 static struct clk ssi_sst_fck = {
1653         .name           = "ssi_sst_fck",
1654         .ops            = &clkops_null,
1655         .parent         = &ssi_ssr_fck,
1656         .fixed_div      = 2,
1657         .recalc         = &omap2_fixed_divisor_recalc,
1658 };
1659
1660
1661
1662 /* CORE_L3_ICK based clocks */
1663
1664 /*
1665  * XXX must add clk_enable/clk_disable for these if standard code won't
1666  * handle it
1667  */
1668 static struct clk core_l3_ick = {
1669         .name           = "core_l3_ick",
1670         .ops            = &clkops_null,
1671         .parent         = &l3_ick,
1672         .init           = &omap2_init_clk_clkdm,
1673         .clkdm_name     = "core_l3_clkdm",
1674         .recalc         = &followparent_recalc,
1675 };
1676
1677 static struct clk hsotgusb_ick = {
1678         .name           = "hsotgusb_ick",
1679         .ops            = &clkops_omap2_dflt_wait,
1680         .parent         = &core_l3_ick,
1681         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1682         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1683         .clkdm_name     = "core_l3_clkdm",
1684         .recalc         = &followparent_recalc,
1685 };
1686
1687 static struct clk sdrc_ick = {
1688         .name           = "sdrc_ick",
1689         .ops            = &clkops_omap2_dflt_wait,
1690         .parent         = &core_l3_ick,
1691         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1692         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1693         .flags          = ENABLE_ON_INIT,
1694         .clkdm_name     = "core_l3_clkdm",
1695         .recalc         = &followparent_recalc,
1696 };
1697
1698 static struct clk gpmc_fck = {
1699         .name           = "gpmc_fck",
1700         .ops            = &clkops_null,
1701         .parent         = &core_l3_ick,
1702         .flags          = ENABLE_ON_INIT, /* huh? */
1703         .clkdm_name     = "core_l3_clkdm",
1704         .recalc         = &followparent_recalc,
1705 };
1706
1707 /* SECURITY_L3_ICK based clocks */
1708
1709 static struct clk security_l3_ick = {
1710         .name           = "security_l3_ick",
1711         .ops            = &clkops_null,
1712         .parent         = &l3_ick,
1713         .recalc         = &followparent_recalc,
1714 };
1715
1716 static struct clk pka_ick = {
1717         .name           = "pka_ick",
1718         .ops            = &clkops_omap2_dflt_wait,
1719         .parent         = &security_l3_ick,
1720         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1721         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1722         .recalc         = &followparent_recalc,
1723 };
1724
1725 /* CORE_L4_ICK based clocks */
1726
1727 static struct clk core_l4_ick = {
1728         .name           = "core_l4_ick",
1729         .ops            = &clkops_null,
1730         .parent         = &l4_ick,
1731         .init           = &omap2_init_clk_clkdm,
1732         .clkdm_name     = "core_l4_clkdm",
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk usbtll_ick = {
1737         .name           = "usbtll_ick",
1738         .ops            = &clkops_omap2_dflt_wait,
1739         .parent         = &core_l4_ick,
1740         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1741         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1742         .clkdm_name     = "core_l4_clkdm",
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk mmchs3_ick = {
1747         .name           = "mmchs_ick",
1748         .ops            = &clkops_omap2_dflt_wait,
1749         .id             = 2,
1750         .parent         = &core_l4_ick,
1751         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1752         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1753         .clkdm_name     = "core_l4_clkdm",
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 /* Intersystem Communication Registers - chassis mode only */
1758 static struct clk icr_ick = {
1759         .name           = "icr_ick",
1760         .ops            = &clkops_omap2_dflt_wait,
1761         .parent         = &core_l4_ick,
1762         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1763         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1764         .clkdm_name     = "core_l4_clkdm",
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk aes2_ick = {
1769         .name           = "aes2_ick",
1770         .ops            = &clkops_omap2_dflt_wait,
1771         .parent         = &core_l4_ick,
1772         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1773         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1774         .clkdm_name     = "core_l4_clkdm",
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk sha12_ick = {
1779         .name           = "sha12_ick",
1780         .ops            = &clkops_omap2_dflt_wait,
1781         .parent         = &core_l4_ick,
1782         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1783         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1784         .clkdm_name     = "core_l4_clkdm",
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk des2_ick = {
1789         .name           = "des2_ick",
1790         .ops            = &clkops_omap2_dflt_wait,
1791         .parent         = &core_l4_ick,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1793         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1794         .clkdm_name     = "core_l4_clkdm",
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk mmchs2_ick = {
1799         .name           = "mmchs_ick",
1800         .ops            = &clkops_omap2_dflt_wait,
1801         .id             = 1,
1802         .parent         = &core_l4_ick,
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1805         .clkdm_name     = "core_l4_clkdm",
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 static struct clk mmchs1_ick = {
1810         .name           = "mmchs_ick",
1811         .ops            = &clkops_omap2_dflt_wait,
1812         .parent         = &core_l4_ick,
1813         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1814         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1815         .clkdm_name     = "core_l4_clkdm",
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk mspro_ick = {
1820         .name           = "mspro_ick",
1821         .ops            = &clkops_omap2_dflt_wait,
1822         .parent         = &core_l4_ick,
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1825         .clkdm_name     = "core_l4_clkdm",
1826         .recalc         = &followparent_recalc,
1827 };
1828
1829 static struct clk hdq_ick = {
1830         .name           = "hdq_ick",
1831         .ops            = &clkops_omap2_dflt_wait,
1832         .parent         = &core_l4_ick,
1833         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1834         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1835         .clkdm_name     = "core_l4_clkdm",
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk mcspi4_ick = {
1840         .name           = "mcspi_ick",
1841         .ops            = &clkops_omap2_dflt_wait,
1842         .id             = 4,
1843         .parent         = &core_l4_ick,
1844         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1845         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1846         .clkdm_name     = "core_l4_clkdm",
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mcspi3_ick = {
1851         .name           = "mcspi_ick",
1852         .ops            = &clkops_omap2_dflt_wait,
1853         .id             = 3,
1854         .parent         = &core_l4_ick,
1855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1856         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1857         .clkdm_name     = "core_l4_clkdm",
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk mcspi2_ick = {
1862         .name           = "mcspi_ick",
1863         .ops            = &clkops_omap2_dflt_wait,
1864         .id             = 2,
1865         .parent         = &core_l4_ick,
1866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1868         .clkdm_name     = "core_l4_clkdm",
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcspi1_ick = {
1873         .name           = "mcspi_ick",
1874         .ops            = &clkops_omap2_dflt_wait,
1875         .id             = 1,
1876         .parent         = &core_l4_ick,
1877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1878         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1879         .clkdm_name     = "core_l4_clkdm",
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk i2c3_ick = {
1884         .name           = "i2c_ick",
1885         .ops            = &clkops_omap2_dflt_wait,
1886         .id             = 3,
1887         .parent         = &core_l4_ick,
1888         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1889         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1890         .clkdm_name     = "core_l4_clkdm",
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk i2c2_ick = {
1895         .name           = "i2c_ick",
1896         .ops            = &clkops_omap2_dflt_wait,
1897         .id             = 2,
1898         .parent         = &core_l4_ick,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1901         .clkdm_name     = "core_l4_clkdm",
1902         .recalc         = &followparent_recalc,
1903 };
1904
1905 static struct clk i2c1_ick = {
1906         .name           = "i2c_ick",
1907         .ops            = &clkops_omap2_dflt_wait,
1908         .id             = 1,
1909         .parent         = &core_l4_ick,
1910         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1911         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1912         .clkdm_name     = "core_l4_clkdm",
1913         .recalc         = &followparent_recalc,
1914 };
1915
1916 static struct clk uart2_ick = {
1917         .name           = "uart2_ick",
1918         .ops            = &clkops_omap2_dflt_wait,
1919         .parent         = &core_l4_ick,
1920         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1922         .clkdm_name     = "core_l4_clkdm",
1923         .recalc         = &followparent_recalc,
1924 };
1925
1926 static struct clk uart1_ick = {
1927         .name           = "uart1_ick",
1928         .ops            = &clkops_omap2_dflt_wait,
1929         .parent         = &core_l4_ick,
1930         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1931         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1932         .clkdm_name     = "core_l4_clkdm",
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk gpt11_ick = {
1937         .name           = "gpt11_ick",
1938         .ops            = &clkops_omap2_dflt_wait,
1939         .parent         = &core_l4_ick,
1940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1942         .clkdm_name     = "core_l4_clkdm",
1943         .recalc         = &followparent_recalc,
1944 };
1945
1946 static struct clk gpt10_ick = {
1947         .name           = "gpt10_ick",
1948         .ops            = &clkops_omap2_dflt_wait,
1949         .parent         = &core_l4_ick,
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1952         .clkdm_name     = "core_l4_clkdm",
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk mcbsp5_ick = {
1957         .name           = "mcbsp_ick",
1958         .ops            = &clkops_omap2_dflt_wait,
1959         .id             = 5,
1960         .parent         = &core_l4_ick,
1961         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1963         .clkdm_name     = "core_l4_clkdm",
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk mcbsp1_ick = {
1968         .name           = "mcbsp_ick",
1969         .ops            = &clkops_omap2_dflt_wait,
1970         .id             = 1,
1971         .parent         = &core_l4_ick,
1972         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1974         .clkdm_name     = "core_l4_clkdm",
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 static struct clk fac_ick = {
1979         .name           = "fac_ick",
1980         .ops            = &clkops_omap2_dflt_wait,
1981         .parent         = &core_l4_ick,
1982         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1984         .clkdm_name     = "core_l4_clkdm",
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk mailboxes_ick = {
1989         .name           = "mailboxes_ick",
1990         .ops            = &clkops_omap2_dflt_wait,
1991         .parent         = &core_l4_ick,
1992         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1994         .clkdm_name     = "core_l4_clkdm",
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk omapctrl_ick = {
1999         .name           = "omapctrl_ick",
2000         .ops            = &clkops_omap2_dflt_wait,
2001         .parent         = &core_l4_ick,
2002         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2004         .flags          = ENABLE_ON_INIT,
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 /* SSI_L4_ICK based clocks */
2009
2010 static struct clk ssi_l4_ick = {
2011         .name           = "ssi_l4_ick",
2012         .ops            = &clkops_null,
2013         .parent         = &l4_ick,
2014         .clkdm_name     = "core_l4_clkdm",
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk ssi_ick = {
2019         .name           = "ssi_ick",
2020         .ops            = &clkops_omap2_dflt,
2021         .parent         = &ssi_l4_ick,
2022         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2024         .clkdm_name     = "core_l4_clkdm",
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2029  * but l4_ick makes more sense to me */
2030
2031 static const struct clksel usb_l4_clksel[] = {
2032         { .parent = &l4_ick, .rates = div2_rates },
2033         { .parent = NULL },
2034 };
2035
2036 static struct clk usb_l4_ick = {
2037         .name           = "usb_l4_ick",
2038         .ops            = &clkops_omap2_dflt_wait,
2039         .parent         = &l4_ick,
2040         .init           = &omap2_init_clksel_parent,
2041         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2043         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2044         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2045         .clksel         = usb_l4_clksel,
2046         .recalc         = &omap2_clksel_recalc,
2047 };
2048
2049 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2050
2051 /* SECURITY_L4_ICK2 based clocks */
2052
2053 static struct clk security_l4_ick2 = {
2054         .name           = "security_l4_ick2",
2055         .ops            = &clkops_null,
2056         .parent         = &l4_ick,
2057         .recalc         = &followparent_recalc,
2058 };
2059
2060 static struct clk aes1_ick = {
2061         .name           = "aes1_ick",
2062         .ops            = &clkops_omap2_dflt_wait,
2063         .parent         = &security_l4_ick2,
2064         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2065         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2066         .recalc         = &followparent_recalc,
2067 };
2068
2069 static struct clk rng_ick = {
2070         .name           = "rng_ick",
2071         .ops            = &clkops_omap2_dflt_wait,
2072         .parent         = &security_l4_ick2,
2073         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2074         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2075         .recalc         = &followparent_recalc,
2076 };
2077
2078 static struct clk sha11_ick = {
2079         .name           = "sha11_ick",
2080         .ops            = &clkops_omap2_dflt_wait,
2081         .parent         = &security_l4_ick2,
2082         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2083         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2084         .recalc         = &followparent_recalc,
2085 };
2086
2087 static struct clk des1_ick = {
2088         .name           = "des1_ick",
2089         .ops            = &clkops_omap2_dflt_wait,
2090         .parent         = &security_l4_ick2,
2091         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2092         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2093         .recalc         = &followparent_recalc,
2094 };
2095
2096 /* DSS */
2097 static const struct clksel dss1_alwon_fck_clksel[] = {
2098         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2099         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2100         { .parent = NULL }
2101 };
2102
2103 static struct clk dss1_alwon_fck = {
2104         .name           = "dss1_alwon_fck",
2105         .ops            = &clkops_omap2_dflt,
2106         .parent         = &dpll4_m4x2_ck,
2107         .init           = &omap2_init_clksel_parent,
2108         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2109         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2110         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2111         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2112         .clksel         = dss1_alwon_fck_clksel,
2113         .clkdm_name     = "dss_clkdm",
2114         .recalc         = &omap2_clksel_recalc,
2115 };
2116
2117 static struct clk dss_tv_fck = {
2118         .name           = "dss_tv_fck",
2119         .ops            = &clkops_omap2_dflt,
2120         .parent         = &omap_54m_fck,
2121         .init           = &omap2_init_clk_clkdm,
2122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2123         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2124         .clkdm_name     = "dss_clkdm",
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk dss_96m_fck = {
2129         .name           = "dss_96m_fck",
2130         .ops            = &clkops_omap2_dflt,
2131         .parent         = &omap_96m_fck,
2132         .init           = &omap2_init_clk_clkdm,
2133         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2134         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2135         .clkdm_name     = "dss_clkdm",
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 static struct clk dss2_alwon_fck = {
2140         .name           = "dss2_alwon_fck",
2141         .ops            = &clkops_omap2_dflt,
2142         .parent         = &sys_ck,
2143         .init           = &omap2_init_clk_clkdm,
2144         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2145         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2146         .clkdm_name     = "dss_clkdm",
2147         .recalc         = &followparent_recalc,
2148 };
2149
2150 static struct clk dss_ick = {
2151         /* Handles both L3 and L4 clocks */
2152         .name           = "dss_ick",
2153         .ops            = &clkops_omap2_dflt,
2154         .parent         = &l4_ick,
2155         .init           = &omap2_init_clk_clkdm,
2156         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2157         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2158         .clkdm_name     = "dss_clkdm",
2159         .recalc         = &followparent_recalc,
2160 };
2161
2162 /* CAM */
2163
2164 static const struct clksel cam_mclk_clksel[] = {
2165         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2166         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2167         { .parent = NULL }
2168 };
2169
2170 static struct clk cam_mclk = {
2171         .name           = "cam_mclk",
2172         .ops            = &clkops_omap2_dflt_wait,
2173         .parent         = &dpll4_m5x2_ck,
2174         .init           = &omap2_init_clksel_parent,
2175         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2176         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2177         .clksel         = cam_mclk_clksel,
2178         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2179         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2180         .clkdm_name     = "cam_clkdm",
2181         .recalc         = &omap2_clksel_recalc,
2182 };
2183
2184 static struct clk cam_ick = {
2185         /* Handles both L3 and L4 clocks */
2186         .name           = "cam_ick",
2187         .ops            = &clkops_omap2_dflt_wait,
2188         .parent         = &l4_ick,
2189         .init           = &omap2_init_clk_clkdm,
2190         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2191         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2192         .clkdm_name     = "cam_clkdm",
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk csi2_96m_fck = {
2197         .name           = "csi2_96m_fck",
2198         .ops            = &clkops_omap2_dflt_wait,
2199         .parent         = &core_96m_fck,
2200         .init           = &omap2_init_clk_clkdm,
2201         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2202         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2203         .clkdm_name     = "cam_clkdm",
2204         .recalc         = &followparent_recalc,
2205 };
2206
2207 /* USBHOST - 3430ES2 only */
2208
2209 static struct clk usbhost_120m_fck = {
2210         .name           = "usbhost_120m_fck",
2211         .ops            = &clkops_omap2_dflt_wait,
2212         .parent         = &omap_120m_fck,
2213         .init           = &omap2_init_clk_clkdm,
2214         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2215         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2216         .clkdm_name     = "usbhost_clkdm",
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk usbhost_48m_fck = {
2221         .name           = "usbhost_48m_fck",
2222         .ops            = &clkops_omap2_dflt_wait,
2223         .parent         = &omap_48m_fck,
2224         .init           = &omap2_init_clk_clkdm,
2225         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2226         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2227         .clkdm_name     = "usbhost_clkdm",
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk usbhost_ick = {
2232         /* Handles both L3 and L4 clocks */
2233         .name           = "usbhost_ick",
2234         .ops            = &clkops_omap2_dflt_wait,
2235         .parent         = &l4_ick,
2236         .init           = &omap2_init_clk_clkdm,
2237         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2238         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2239         .clkdm_name     = "usbhost_clkdm",
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 /* WKUP */
2244
2245 static const struct clksel_rate usim_96m_rates[] = {
2246         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2247         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2248         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2249         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2250         { .div = 0 },
2251 };
2252
2253 static const struct clksel_rate usim_120m_rates[] = {
2254         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2255         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2256         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2257         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2258         { .div = 0 },
2259 };
2260
2261 static const struct clksel usim_clksel[] = {
2262         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2263         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2264         { .parent = &sys_ck,            .rates = div2_rates },
2265         { .parent = NULL },
2266 };
2267
2268 /* 3430ES2 only */
2269 static struct clk usim_fck = {
2270         .name           = "usim_fck",
2271         .ops            = &clkops_omap2_dflt_wait,
2272         .init           = &omap2_init_clksel_parent,
2273         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2274         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2275         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2276         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2277         .clksel         = usim_clksel,
2278         .recalc         = &omap2_clksel_recalc,
2279 };
2280
2281 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2282 static struct clk gpt1_fck = {
2283         .name           = "gpt1_fck",
2284         .ops            = &clkops_omap2_dflt_wait,
2285         .init           = &omap2_init_clksel_parent,
2286         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2287         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2288         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2289         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2290         .clksel         = omap343x_gpt_clksel,
2291         .clkdm_name     = "wkup_clkdm",
2292         .recalc         = &omap2_clksel_recalc,
2293 };
2294
2295 static struct clk wkup_32k_fck = {
2296         .name           = "wkup_32k_fck",
2297         .ops            = &clkops_null,
2298         .init           = &omap2_init_clk_clkdm,
2299         .parent         = &omap_32k_fck,
2300         .clkdm_name     = "wkup_clkdm",
2301         .recalc         = &followparent_recalc,
2302 };
2303
2304 static struct clk gpio1_dbck = {
2305         .name           = "gpio1_dbck",
2306         .ops            = &clkops_omap2_dflt_wait,
2307         .parent         = &wkup_32k_fck,
2308         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2309         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2310         .clkdm_name     = "wkup_clkdm",
2311         .recalc         = &followparent_recalc,
2312 };
2313
2314 static struct clk wdt2_fck = {
2315         .name           = "wdt2_fck",
2316         .ops            = &clkops_omap2_dflt_wait,
2317         .parent         = &wkup_32k_fck,
2318         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2319         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2320         .clkdm_name     = "wkup_clkdm",
2321         .recalc         = &followparent_recalc,
2322 };
2323
2324 static struct clk wkup_l4_ick = {
2325         .name           = "wkup_l4_ick",
2326         .ops            = &clkops_null,
2327         .parent         = &sys_ck,
2328         .clkdm_name     = "wkup_clkdm",
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 /* 3430ES2 only */
2333 /* Never specifically named in the TRM, so we have to infer a likely name */
2334 static struct clk usim_ick = {
2335         .name           = "usim_ick",
2336         .ops            = &clkops_omap2_dflt_wait,
2337         .parent         = &wkup_l4_ick,
2338         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2339         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2340         .clkdm_name     = "wkup_clkdm",
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk wdt2_ick = {
2345         .name           = "wdt2_ick",
2346         .ops            = &clkops_omap2_dflt_wait,
2347         .parent         = &wkup_l4_ick,
2348         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2349         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2350         .clkdm_name     = "wkup_clkdm",
2351         .recalc         = &followparent_recalc,
2352 };
2353
2354 static struct clk wdt1_ick = {
2355         .name           = "wdt1_ick",
2356         .ops            = &clkops_omap2_dflt_wait,
2357         .parent         = &wkup_l4_ick,
2358         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2359         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2360         .clkdm_name     = "wkup_clkdm",
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk gpio1_ick = {
2365         .name           = "gpio1_ick",
2366         .ops            = &clkops_omap2_dflt_wait,
2367         .parent         = &wkup_l4_ick,
2368         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2369         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2370         .clkdm_name     = "wkup_clkdm",
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk omap_32ksync_ick = {
2375         .name           = "omap_32ksync_ick",
2376         .ops            = &clkops_omap2_dflt_wait,
2377         .parent         = &wkup_l4_ick,
2378         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2379         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2380         .clkdm_name     = "wkup_clkdm",
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384 /* XXX This clock no longer exists in 3430 TRM rev F */
2385 static struct clk gpt12_ick = {
2386         .name           = "gpt12_ick",
2387         .ops            = &clkops_omap2_dflt_wait,
2388         .parent         = &wkup_l4_ick,
2389         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2390         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2391         .clkdm_name     = "wkup_clkdm",
2392         .recalc         = &followparent_recalc,
2393 };
2394
2395 static struct clk gpt1_ick = {
2396         .name           = "gpt1_ick",
2397         .ops            = &clkops_omap2_dflt_wait,
2398         .parent         = &wkup_l4_ick,
2399         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2400         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2401         .clkdm_name     = "wkup_clkdm",
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405
2406
2407 /* PER clock domain */
2408
2409 static struct clk per_96m_fck = {
2410         .name           = "per_96m_fck",
2411         .ops            = &clkops_null,
2412         .parent         = &omap_96m_alwon_fck,
2413         .init           = &omap2_init_clk_clkdm,
2414         .clkdm_name     = "per_clkdm",
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk per_48m_fck = {
2419         .name           = "per_48m_fck",
2420         .ops            = &clkops_null,
2421         .parent         = &omap_48m_fck,
2422         .init           = &omap2_init_clk_clkdm,
2423         .clkdm_name     = "per_clkdm",
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk uart3_fck = {
2428         .name           = "uart3_fck",
2429         .ops            = &clkops_omap2_dflt_wait,
2430         .parent         = &per_48m_fck,
2431         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2432         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2433         .clkdm_name     = "per_clkdm",
2434         .recalc         = &followparent_recalc,
2435 };
2436
2437 static struct clk gpt2_fck = {
2438         .name           = "gpt2_fck",
2439         .ops            = &clkops_omap2_dflt_wait,
2440         .init           = &omap2_init_clksel_parent,
2441         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2442         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2443         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2444         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2445         .clksel         = omap343x_gpt_clksel,
2446         .clkdm_name     = "per_clkdm",
2447         .recalc         = &omap2_clksel_recalc,
2448 };
2449
2450 static struct clk gpt3_fck = {
2451         .name           = "gpt3_fck",
2452         .ops            = &clkops_omap2_dflt_wait,
2453         .init           = &omap2_init_clksel_parent,
2454         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2455         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2456         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2457         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2458         .clksel         = omap343x_gpt_clksel,
2459         .clkdm_name     = "per_clkdm",
2460         .recalc         = &omap2_clksel_recalc,
2461 };
2462
2463 static struct clk gpt4_fck = {
2464         .name           = "gpt4_fck",
2465         .ops            = &clkops_omap2_dflt_wait,
2466         .init           = &omap2_init_clksel_parent,
2467         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2469         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2470         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2471         .clksel         = omap343x_gpt_clksel,
2472         .clkdm_name     = "per_clkdm",
2473         .recalc         = &omap2_clksel_recalc,
2474 };
2475
2476 static struct clk gpt5_fck = {
2477         .name           = "gpt5_fck",
2478         .ops            = &clkops_omap2_dflt_wait,
2479         .init           = &omap2_init_clksel_parent,
2480         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2481         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2482         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2483         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2484         .clksel         = omap343x_gpt_clksel,
2485         .clkdm_name     = "per_clkdm",
2486         .recalc         = &omap2_clksel_recalc,
2487 };
2488
2489 static struct clk gpt6_fck = {
2490         .name           = "gpt6_fck",
2491         .ops            = &clkops_omap2_dflt_wait,
2492         .init           = &omap2_init_clksel_parent,
2493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2495         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2496         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2497         .clksel         = omap343x_gpt_clksel,
2498         .clkdm_name     = "per_clkdm",
2499         .recalc         = &omap2_clksel_recalc,
2500 };
2501
2502 static struct clk gpt7_fck = {
2503         .name           = "gpt7_fck",
2504         .ops            = &clkops_omap2_dflt_wait,
2505         .init           = &omap2_init_clksel_parent,
2506         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2508         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2509         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2510         .clksel         = omap343x_gpt_clksel,
2511         .clkdm_name     = "per_clkdm",
2512         .recalc         = &omap2_clksel_recalc,
2513 };
2514
2515 static struct clk gpt8_fck = {
2516         .name           = "gpt8_fck",
2517         .ops            = &clkops_omap2_dflt_wait,
2518         .init           = &omap2_init_clksel_parent,
2519         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2520         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2521         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2522         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2523         .clksel         = omap343x_gpt_clksel,
2524         .clkdm_name     = "per_clkdm",
2525         .recalc         = &omap2_clksel_recalc,
2526 };
2527
2528 static struct clk gpt9_fck = {
2529         .name           = "gpt9_fck",
2530         .ops            = &clkops_omap2_dflt_wait,
2531         .init           = &omap2_init_clksel_parent,
2532         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2533         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2534         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2535         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2536         .clksel         = omap343x_gpt_clksel,
2537         .clkdm_name     = "per_clkdm",
2538         .recalc         = &omap2_clksel_recalc,
2539 };
2540
2541 static struct clk per_32k_alwon_fck = {
2542         .name           = "per_32k_alwon_fck",
2543         .ops            = &clkops_null,
2544         .parent         = &omap_32k_fck,
2545         .clkdm_name     = "per_clkdm",
2546         .recalc         = &followparent_recalc,
2547 };
2548
2549 static struct clk gpio6_dbck = {
2550         .name           = "gpio6_dbck",
2551         .ops            = &clkops_omap2_dflt_wait,
2552         .parent         = &per_32k_alwon_fck,
2553         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2555         .clkdm_name     = "per_clkdm",
2556         .recalc         = &followparent_recalc,
2557 };
2558
2559 static struct clk gpio5_dbck = {
2560         .name           = "gpio5_dbck",
2561         .ops            = &clkops_omap2_dflt_wait,
2562         .parent         = &per_32k_alwon_fck,
2563         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2565         .clkdm_name     = "per_clkdm",
2566         .recalc         = &followparent_recalc,
2567 };
2568
2569 static struct clk gpio4_dbck = {
2570         .name           = "gpio4_dbck",
2571         .ops            = &clkops_omap2_dflt_wait,
2572         .parent         = &per_32k_alwon_fck,
2573         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2575         .clkdm_name     = "per_clkdm",
2576         .recalc         = &followparent_recalc,
2577 };
2578
2579 static struct clk gpio3_dbck = {
2580         .name           = "gpio3_dbck",
2581         .ops            = &clkops_omap2_dflt_wait,
2582         .parent         = &per_32k_alwon_fck,
2583         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2584         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2585         .clkdm_name     = "per_clkdm",
2586         .recalc         = &followparent_recalc,
2587 };
2588
2589 static struct clk gpio2_dbck = {
2590         .name           = "gpio2_dbck",
2591         .ops            = &clkops_omap2_dflt_wait,
2592         .parent         = &per_32k_alwon_fck,
2593         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2594         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2595         .clkdm_name     = "per_clkdm",
2596         .recalc         = &followparent_recalc,
2597 };
2598
2599 static struct clk wdt3_fck = {
2600         .name           = "wdt3_fck",
2601         .ops            = &clkops_omap2_dflt_wait,
2602         .parent         = &per_32k_alwon_fck,
2603         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2604         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2605         .clkdm_name     = "per_clkdm",
2606         .recalc         = &followparent_recalc,
2607 };
2608
2609 static struct clk per_l4_ick = {
2610         .name           = "per_l4_ick",
2611         .ops            = &clkops_null,
2612         .parent         = &l4_ick,
2613         .clkdm_name     = "per_clkdm",
2614         .recalc         = &followparent_recalc,
2615 };
2616
2617 static struct clk gpio6_ick = {
2618         .name           = "gpio6_ick",
2619         .ops            = &clkops_omap2_dflt_wait,
2620         .parent         = &per_l4_ick,
2621         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2622         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2623         .clkdm_name     = "per_clkdm",
2624         .recalc         = &followparent_recalc,
2625 };
2626
2627 static struct clk gpio5_ick = {
2628         .name           = "gpio5_ick",
2629         .ops            = &clkops_omap2_dflt_wait,
2630         .parent         = &per_l4_ick,
2631         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2632         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2633         .clkdm_name     = "per_clkdm",
2634         .recalc         = &followparent_recalc,
2635 };
2636
2637 static struct clk gpio4_ick = {
2638         .name           = "gpio4_ick",
2639         .ops            = &clkops_omap2_dflt_wait,
2640         .parent         = &per_l4_ick,
2641         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2642         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2643         .clkdm_name     = "per_clkdm",
2644         .recalc         = &followparent_recalc,
2645 };
2646
2647 static struct clk gpio3_ick = {
2648         .name           = "gpio3_ick",
2649         .ops            = &clkops_omap2_dflt_wait,
2650         .parent         = &per_l4_ick,
2651         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2652         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2653         .clkdm_name     = "per_clkdm",
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk gpio2_ick = {
2658         .name           = "gpio2_ick",
2659         .ops            = &clkops_omap2_dflt_wait,
2660         .parent         = &per_l4_ick,
2661         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2662         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2663         .clkdm_name     = "per_clkdm",
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk wdt3_ick = {
2668         .name           = "wdt3_ick",
2669         .ops            = &clkops_omap2_dflt_wait,
2670         .parent         = &per_l4_ick,
2671         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2672         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2673         .clkdm_name     = "per_clkdm",
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk uart3_ick = {
2678         .name           = "uart3_ick",
2679         .ops            = &clkops_omap2_dflt_wait,
2680         .parent         = &per_l4_ick,
2681         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2682         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2683         .clkdm_name     = "per_clkdm",
2684         .recalc         = &followparent_recalc,
2685 };
2686
2687 static struct clk gpt9_ick = {
2688         .name           = "gpt9_ick",
2689         .ops            = &clkops_omap2_dflt_wait,
2690         .parent         = &per_l4_ick,
2691         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2692         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2693         .clkdm_name     = "per_clkdm",
2694         .recalc         = &followparent_recalc,
2695 };
2696
2697 static struct clk gpt8_ick = {
2698         .name           = "gpt8_ick",
2699         .ops            = &clkops_omap2_dflt_wait,
2700         .parent         = &per_l4_ick,
2701         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2702         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2703         .clkdm_name     = "per_clkdm",
2704         .recalc         = &followparent_recalc,
2705 };
2706
2707 static struct clk gpt7_ick = {
2708         .name           = "gpt7_ick",
2709         .ops            = &clkops_omap2_dflt_wait,
2710         .parent         = &per_l4_ick,
2711         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2712         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2713         .clkdm_name     = "per_clkdm",
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk gpt6_ick = {
2718         .name           = "gpt6_ick",
2719         .ops            = &clkops_omap2_dflt_wait,
2720         .parent         = &per_l4_ick,
2721         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2722         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2723         .clkdm_name     = "per_clkdm",
2724         .recalc         = &followparent_recalc,
2725 };
2726
2727 static struct clk gpt5_ick = {
2728         .name           = "gpt5_ick",
2729         .ops            = &clkops_omap2_dflt_wait,
2730         .parent         = &per_l4_ick,
2731         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2732         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2733         .clkdm_name     = "per_clkdm",
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk gpt4_ick = {
2738         .name           = "gpt4_ick",
2739         .ops            = &clkops_omap2_dflt_wait,
2740         .parent         = &per_l4_ick,
2741         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2743         .clkdm_name     = "per_clkdm",
2744         .recalc         = &followparent_recalc,
2745 };
2746
2747 static struct clk gpt3_ick = {
2748         .name           = "gpt3_ick",
2749         .ops            = &clkops_omap2_dflt_wait,
2750         .parent         = &per_l4_ick,
2751         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2753         .clkdm_name     = "per_clkdm",
2754         .recalc         = &followparent_recalc,
2755 };
2756
2757 static struct clk gpt2_ick = {
2758         .name           = "gpt2_ick",
2759         .ops            = &clkops_omap2_dflt_wait,
2760         .parent         = &per_l4_ick,
2761         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2762         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2763         .clkdm_name     = "per_clkdm",
2764         .recalc         = &followparent_recalc,
2765 };
2766
2767 static struct clk mcbsp2_ick = {
2768         .name           = "mcbsp_ick",
2769         .ops            = &clkops_omap2_dflt_wait,
2770         .id             = 2,
2771         .parent         = &per_l4_ick,
2772         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2774         .clkdm_name     = "per_clkdm",
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk mcbsp3_ick = {
2779         .name           = "mcbsp_ick",
2780         .ops            = &clkops_omap2_dflt_wait,
2781         .id             = 3,
2782         .parent         = &per_l4_ick,
2783         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2784         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2785         .clkdm_name     = "per_clkdm",
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk mcbsp4_ick = {
2790         .name           = "mcbsp_ick",
2791         .ops            = &clkops_omap2_dflt_wait,
2792         .id             = 4,
2793         .parent         = &per_l4_ick,
2794         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2795         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2796         .clkdm_name     = "per_clkdm",
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 static const struct clksel mcbsp_234_clksel[] = {
2801         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2802         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2803         { .parent = NULL }
2804 };
2805
2806 static struct clk mcbsp2_fck = {
2807         .name           = "mcbsp_fck",
2808         .ops            = &clkops_omap2_dflt_wait,
2809         .id             = 2,
2810         .init           = &omap2_init_clksel_parent,
2811         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2812         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2813         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2814         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2815         .clksel         = mcbsp_234_clksel,
2816         .clkdm_name     = "per_clkdm",
2817         .recalc         = &omap2_clksel_recalc,
2818 };
2819
2820 static struct clk mcbsp3_fck = {
2821         .name           = "mcbsp_fck",
2822         .ops            = &clkops_omap2_dflt_wait,
2823         .id             = 3,
2824         .init           = &omap2_init_clksel_parent,
2825         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2826         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2827         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2828         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2829         .clksel         = mcbsp_234_clksel,
2830         .clkdm_name     = "per_clkdm",
2831         .recalc         = &omap2_clksel_recalc,
2832 };
2833
2834 static struct clk mcbsp4_fck = {
2835         .name           = "mcbsp_fck",
2836         .ops            = &clkops_omap2_dflt_wait,
2837         .id             = 4,
2838         .init           = &omap2_init_clksel_parent,
2839         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2840         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2841         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2842         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2843         .clksel         = mcbsp_234_clksel,
2844         .clkdm_name     = "per_clkdm",
2845         .recalc         = &omap2_clksel_recalc,
2846 };
2847
2848 /* EMU clocks */
2849
2850 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2851
2852 static const struct clksel_rate emu_src_sys_rates[] = {
2853         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2854         { .div = 0 },
2855 };
2856
2857 static const struct clksel_rate emu_src_core_rates[] = {
2858         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2859         { .div = 0 },
2860 };
2861
2862 static const struct clksel_rate emu_src_per_rates[] = {
2863         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2864         { .div = 0 },
2865 };
2866
2867 static const struct clksel_rate emu_src_mpu_rates[] = {
2868         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2869         { .div = 0 },
2870 };
2871
2872 static const struct clksel emu_src_clksel[] = {
2873         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2874         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2875         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2876         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2877         { .parent = NULL },
2878 };
2879
2880 /*
2881  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2882  * to switch the source of some of the EMU clocks.
2883  * XXX Are there CLKEN bits for these EMU clks?
2884  */
2885 static struct clk emu_src_ck = {
2886         .name           = "emu_src_ck",
2887         .ops            = &clkops_null,
2888         .init           = &omap2_init_clksel_parent,
2889         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2890         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2891         .clksel         = emu_src_clksel,
2892         .clkdm_name     = "emu_clkdm",
2893         .recalc         = &omap2_clksel_recalc,
2894 };
2895
2896 static const struct clksel_rate pclk_emu_rates[] = {
2897         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2898         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2899         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2900         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2901         { .div = 0 },
2902 };
2903
2904 static const struct clksel pclk_emu_clksel[] = {
2905         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2906         { .parent = NULL },
2907 };
2908
2909 static struct clk pclk_fck = {
2910         .name           = "pclk_fck",
2911         .ops            = &clkops_null,
2912         .init           = &omap2_init_clksel_parent,
2913         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2914         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2915         .clksel         = pclk_emu_clksel,
2916         .clkdm_name     = "emu_clkdm",
2917         .recalc         = &omap2_clksel_recalc,
2918 };
2919
2920 static const struct clksel_rate pclkx2_emu_rates[] = {
2921         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2922         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2923         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2924         { .div = 0 },
2925 };
2926
2927 static const struct clksel pclkx2_emu_clksel[] = {
2928         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2929         { .parent = NULL },
2930 };
2931
2932 static struct clk pclkx2_fck = {
2933         .name           = "pclkx2_fck",
2934         .ops            = &clkops_null,
2935         .init           = &omap2_init_clksel_parent,
2936         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2937         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2938         .clksel         = pclkx2_emu_clksel,
2939         .clkdm_name     = "emu_clkdm",
2940         .recalc         = &omap2_clksel_recalc,
2941 };
2942
2943 static const struct clksel atclk_emu_clksel[] = {
2944         { .parent = &emu_src_ck, .rates = div2_rates },
2945         { .parent = NULL },
2946 };
2947
2948 static struct clk atclk_fck = {
2949         .name           = "atclk_fck",
2950         .ops            = &clkops_null,
2951         .init           = &omap2_init_clksel_parent,
2952         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2953         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2954         .clksel         = atclk_emu_clksel,
2955         .clkdm_name     = "emu_clkdm",
2956         .recalc         = &omap2_clksel_recalc,
2957 };
2958
2959 static struct clk traceclk_src_fck = {
2960         .name           = "traceclk_src_fck",
2961         .ops            = &clkops_null,
2962         .init           = &omap2_init_clksel_parent,
2963         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2964         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2965         .clksel         = emu_src_clksel,
2966         .clkdm_name     = "emu_clkdm",
2967         .recalc         = &omap2_clksel_recalc,
2968 };
2969
2970 static const struct clksel_rate traceclk_rates[] = {
2971         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2972         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2973         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2974         { .div = 0 },
2975 };
2976
2977 static const struct clksel traceclk_clksel[] = {
2978         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2979         { .parent = NULL },
2980 };
2981
2982 static struct clk traceclk_fck = {
2983         .name           = "traceclk_fck",
2984         .ops            = &clkops_null,
2985         .init           = &omap2_init_clksel_parent,
2986         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2987         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2988         .clksel         = traceclk_clksel,
2989         .clkdm_name     = "emu_clkdm",
2990         .recalc         = &omap2_clksel_recalc,
2991 };
2992
2993 /* SR clocks */
2994
2995 /* SmartReflex fclk (VDD1) */
2996 static struct clk sr1_fck = {
2997         .name           = "sr1_fck",
2998         .ops            = &clkops_omap2_dflt_wait,
2999         .parent         = &sys_ck,
3000         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3001         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3002         .recalc         = &followparent_recalc,
3003 };
3004
3005 /* SmartReflex fclk (VDD2) */
3006 static struct clk sr2_fck = {
3007         .name           = "sr2_fck",
3008         .ops            = &clkops_omap2_dflt_wait,
3009         .parent         = &sys_ck,
3010         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3011         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3012         .recalc         = &followparent_recalc,
3013 };
3014
3015 static struct clk sr_l4_ick = {
3016         .name           = "sr_l4_ick",
3017         .ops            = &clkops_null, /* RMK: missing? */
3018         .parent         = &l4_ick,
3019         .clkdm_name     = "core_l4_clkdm",
3020         .recalc         = &followparent_recalc,
3021 };
3022
3023 /* SECURE_32K_FCK clocks */
3024
3025 /* XXX This clock no longer exists in 3430 TRM rev F */
3026 static struct clk gpt12_fck = {
3027         .name           = "gpt12_fck",
3028         .ops            = &clkops_null,
3029         .parent         = &secure_32k_fck,
3030         .recalc         = &followparent_recalc,
3031 };
3032
3033 static struct clk wdt1_fck = {
3034         .name           = "wdt1_fck",
3035         .ops            = &clkops_null,
3036         .parent         = &secure_32k_fck,
3037         .recalc         = &followparent_recalc,
3038 };
3039
3040 #endif