drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVS33                  (0x7 << 9)
  59 #define SDVS_MASK               0x00000E00
  60 #define SDVSCLR                 0xFFFFF1FF
  61 #define SDVSDET                 0x00000400
  62 #define AUTOIDLE                0x1
  63 #define SDBP                    (1 << 8)
  64 #define DTO                     0xe
  65 #define ICE                     0x1
  66 #define ICS                     0x2
  67 #define CEN                     (1 << 2)
  68 #define CLKD_MASK               0x0000FFC0
  69 #define CLKD_SHIFT              6
  70 #define DTO_MASK                0x000F0000
  71 #define DTO_SHIFT               16
  72 #define INT_EN_MASK             0x307F0033
  73 #define INIT_STREAM             (1 << 1)
  74 #define DP_SELECT               (1 << 21)
  75 #define DDIR                    (1 << 4)
  76 #define DMA_EN                  0x1
  77 #define MSBS                    (1 << 5)
  78 #define BCE                     (1 << 1)
  79 #define FOUR_BIT                (1 << 1)
  80 #define CC                      0x1
  81 #define TC                      0x02
  82 #define OD                      0x1
  83 #define ERR                     (1 << 15)
  84 #define CMD_TIMEOUT             (1 << 16)
  85 #define DATA_TIMEOUT            (1 << 20)
  86 #define CMD_CRC                 (1 << 17)
  87 #define DATA_CRC                (1 << 21)
  88 #define CARD_ERR                (1 << 28)
  89 #define STAT_CLEAR              0xFFFFFFFF
  90 #define INIT_STREAM_CMD         0x00000000
  91 #define DUAL_VOLT_OCR_BIT       7
  92 #define SRC                     (1 << 25)
  93 #define SRD                     (1 << 26)
  94
  95 /*
  96  * FIXME: Most likely all the data using these _DEVID defines should come
  97  * from the platform_data, or implemented in controller and slot specific
  98  * functions.
  99  */
 100 #define OMAP_MMC1_DEVID         0
 101 #define OMAP_MMC2_DEVID         1
 102
 103 #define OMAP_MMC_DATADIR_NONE   0
 104 #define OMAP_MMC_DATADIR_READ   1
 105 #define OMAP_MMC_DATADIR_WRITE  2
 106 #define MMC_TIMEOUT_MS          20
 107 #define OMAP_MMC_MASTER_CLOCK   96000000
 108 #define DRIVER_NAME             "mmci-omap-hs"
 109
 110 /*
 111  * One controller can have multiple slots, like on some omap boards using
 112  * omap.c controller driver. Luckily this is not currently done on any known
 113  * omap_hsmmc.c device.
 114  */
 115 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 116
 117 /*
 118  * MMC Host controller read/write API's
 119  */
 120 #define OMAP_HSMMC_READ(base, reg)      \
 121         __raw_readl((base) + OMAP_HSMMC_##reg)
 122
 123 #define OMAP_HSMMC_WRITE(base, reg, val) \
 124         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 125
 126 struct mmc_omap_host {
 127         struct  device          *dev;
 128         struct  mmc_host        *mmc;
 129         struct  mmc_request     *mrq;
 130         struct  mmc_command     *cmd;
 131         struct  mmc_data        *data;
 132         struct  clk             *fclk;
 133         struct  clk             *iclk;
 134         struct  clk             *dbclk;
 135         struct  semaphore       sem;
 136         struct  work_struct     mmc_carddetect_work;
 137         void    __iomem         *base;
 138         resource_size_t         mapbase;
 139         unsigned int            id;
 140         unsigned int            dma_len;
 141         unsigned int            dma_dir;
 142         unsigned char           bus_mode;
 143         unsigned char           datadir;
 144         u32                     *buffer;
 145         u32                     bytesleft;
 146         int                     suspended;
 147         int                     irq;
 148         int                     carddetect;
 149         int                     use_dma, dma_ch;
 150         int                     initstr;
 151         int                     slot_id;
 152         int                     dbclk_enabled;
 153         int                     response_busy;
 154         struct  omap_mmc_platform_data  *pdata;
 155 };
 156
 157 /*
 158  * Stop clock to the card
 159  */
 160 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 161 {
 162         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 163                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 164         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 165                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 166 }
 167
 168 /*
 169  * Send init stream sequence to card
 170  * before sending IDLE command
 171  */
 172 static void send_init_stream(struct mmc_omap_host *host)
 173 {
 174         int reg = 0;
 175         unsigned long timeout;
 176
 177         disable_irq(host->irq);
 178         OMAP_HSMMC_WRITE(host->base, CON,
 179                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 180         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 181
 182         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 183         while ((reg != CC) && time_before(jiffies, timeout))
 184                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 185
 186         OMAP_HSMMC_WRITE(host->base, CON,
 187                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 188         enable_irq(host->irq);
 189 }
 190
 191 static inline
 192 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 193 {
 194         int r = 1;
 195
 196         if (host->pdata->slots[host->slot_id].get_cover_state)
 197                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 198                         host->slot_id);
 199         return r;
 200 }
 201
 202 static ssize_t
 203 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 204                            char *buf)
 205 {
 206         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 207         struct mmc_omap_host *host = mmc_priv(mmc);
 208
 209         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 210                        "open");
 211 }
 212
 213 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 214
 215 static ssize_t
 216 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 217                         char *buf)
 218 {
 219         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 220         struct mmc_omap_host *host = mmc_priv(mmc);
 221         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 222
 223         return sprintf(buf, "slot:%s\n", slot.name);
 224 }
 225
 226 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 227
 228 /*
 229  * Configure the response type and send the cmd.
 230  */
 231 static void
 232 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 233         struct mmc_data *data)
 234 {
 235         int cmdreg = 0, resptype = 0, cmdtype = 0;
 236
 237         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 238                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 239         host->cmd = cmd;
 240
 241         /*
 242          * Clear status bits and enable interrupts
 243          */
 244         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 245         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 246         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 247
 248         host->response_busy = 0;
 249         if (cmd->flags & MMC_RSP_PRESENT) {
 250                 if (cmd->flags & MMC_RSP_136)
 251                         resptype = 1;
 252                 else if (cmd->flags & MMC_RSP_BUSY) {
 253                         resptype = 3;
 254                         host->response_busy = 1;
 255                 } else
 256                         resptype = 2;
 257         }
 258
 259         /*
 260          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 261          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 262          * a val of 0x3, rest 0x0.
 263          */
 264         if (cmd == host->mrq->stop)
 265                 cmdtype = 0x3;
 266
 267         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 268
 269         if (data) {
 270                 cmdreg |= DP_SELECT | MSBS | BCE;
 271                 if (data->flags & MMC_DATA_READ)
 272                         cmdreg |= DDIR;
 273                 else
 274                         cmdreg &= ~(DDIR);
 275         }
 276
 277         if (host->use_dma)
 278                 cmdreg |= DMA_EN;
 279
 280         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 281         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 282 }
 283
 284 /*
 285  * Notify the transfer complete to MMC core
 286  */
 287 static void
 288 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 289 {
 290         if (!data) {
 291                 struct mmc_request *mrq = host->mrq;
 292
 293                 host->mrq = NULL;
 294                 mmc_omap_fclk_lazy_disable(host);
 295                 mmc_request_done(host->mmc, mrq);
 296                 return;
 297         }
 298
 299         host->data = NULL;
 300
 301         if (host->use_dma && host->dma_ch != -1)
 302                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 303                         host->dma_dir);
 304
 305         host->datadir = OMAP_MMC_DATADIR_NONE;
 306
 307         if (!data->error)
 308                 data->bytes_xfered += data->blocks * (data->blksz);
 309         else
 310                 data->bytes_xfered = 0;
 311
 312         if (!data->stop) {
 313                 host->mrq = NULL;
 314                 mmc_request_done(host->mmc, data->mrq);
 315                 return;
 316         }
 317         mmc_omap_start_command(host, data->stop, NULL);
 318 }
 319
 320 /*
 321  * Notify the core about command completion
 322  */
 323 static void
 324 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 325 {
 326         host->cmd = NULL;
 327
 328         if (cmd->flags & MMC_RSP_PRESENT) {
 329                 if (cmd->flags & MMC_RSP_136) {
 330                         /* response type 2 */
 331                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 332                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 333                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 334                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 335                 } else {
 336                         /* response types 1, 1b, 3, 4, 5, 6 */
 337                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 338                 }
 339         }
 340         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 341                 host->mrq = NULL;
 342                 mmc_request_done(host->mmc, cmd->mrq);
 343         }
 344 }
 345
 346 /*
 347  * DMA clean up for command errors
 348  */
 349 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 350 {
 351         host->data->error = errno;
 352
 353         if (host->use_dma && host->dma_ch != -1) {
 354                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 355                         host->dma_dir);
 356                 omap_free_dma(host->dma_ch);
 357                 host->dma_ch = -1;
 358                 up(&host->sem);
 359         }
 360         host->data = NULL;
 361         host->datadir = OMAP_MMC_DATADIR_NONE;
 362 }
 363
 364 /*
 365  * Readable error output
 366  */
 367 #ifdef CONFIG_MMC_DEBUG
 368 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 369 {
 370         /* --- means reserved bit without definition at documentation */
 371         static const char *mmc_omap_status_bits[] = {
 372                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 373                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 374                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 375                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 376         };
 377         char res[256];
 378         char *buf = res;
 379         int len, i;
 380
 381         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 382         buf += len;
 383
 384         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 385                 if (status & (1 << i)) {
 386                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 387                         buf += len;
 388                 }
 389
 390         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 391 }
 392 #endif  /* CONFIG_MMC_DEBUG */
 393
 394 /*
 395  * MMC controller internal state machines reset
 396  *
 397  * Used to reset command or data internal state machines, using respectively
 398  *  SRC or SRD bit of SYSCTL register
 399  * Can be called from interrupt context
 400  */
 401 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 402                 unsigned long bit)
 403 {
 404         unsigned long i = 0;
 405         unsigned long limit = (loops_per_jiffy *
 406                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 407
 408         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 409                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 410
 411         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 412                 (i++ < limit))
 413                 cpu_relax();
 414
 415         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 416                 dev_err(mmc_dev(host->mmc),
 417                         "Timeout waiting on controller reset in %s\n",
 418                         __func__);
 419 }
 420
 421 /*
 422  * MMC controller IRQ handler
 423  */
 424 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 425 {
 426         struct mmc_omap_host *host = dev_id;
 427         struct mmc_data *data;
 428         int end_cmd = 0, end_trans = 0, status;
 429
 430         if (host->mrq == NULL) {
 431                 OMAP_HSMMC_WRITE(host->base, STAT,
 432                         OMAP_HSMMC_READ(host->base, STAT));
 433                 return IRQ_HANDLED;
 434         }
 435
 436         data = host->data;
 437         status = OMAP_HSMMC_READ(host->base, STAT);
 438         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 439
 440         if (status & ERR) {
 441 #ifdef CONFIG_MMC_DEBUG
 442                 mmc_omap_report_irq(host, status);
 443 #endif
 444                 if ((status & CMD_TIMEOUT) ||
 445                         (status & CMD_CRC)) {
 446                         if (host->cmd) {
 447                                 if (status & CMD_TIMEOUT) {
 448                                         mmc_omap_reset_controller_fsm(host, SRC);
 449                                         host->cmd->error = -ETIMEDOUT;
 450                                 } else {
 451                                         host->cmd->error = -EILSEQ;
 452                                 }
 453                                 end_cmd = 1;
 454                         }
 455                         if (host->data || host->response_busy) {
 456                                 if (host->data)
 457                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 458                                 host->response_busy = 0;
 459                                 mmc_omap_reset_controller_fsm(host, SRD);
 460                         }
 461                 }
 462                 if ((status & DATA_TIMEOUT) ||
 463                         (status & DATA_CRC)) {
 464                         if (host->data || host->response_busy) {
 465                                 int err = (status & DATA_TIMEOUT) ?
 466                                                 -ETIMEDOUT : -EILSEQ;
 467
 468                                 if (host->data)
 469                                         mmc_dma_cleanup(host, err);
 470                                 else
 471                                         host->mrq->cmd->error = err;
 472                                 host->response_busy = 0;
 473                                 mmc_omap_reset_controller_fsm(host, SRD);
 474                                 end_trans = 1;
 475                         }
 476                 }
 477                 if (status & CARD_ERR) {
 478                         dev_dbg(mmc_dev(host->mmc),
 479                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 480                         if (host->cmd)
 481                                 end_cmd = 1;
 482                         if (host->data)
 483                                 end_trans = 1;
 484                 }
 485         }
 486
 487         OMAP_HSMMC_WRITE(host->base, STAT, status);
 488
 489         if (end_cmd || (status & CC))
 490                 mmc_omap_cmd_done(host, host->cmd);
 491         if (end_trans || (status & TC))
 492                 mmc_omap_xfer_done(host, data);
 493
 494         return IRQ_HANDLED;
 495 }
 496
 497 /*
 498  * Switch MMC interface voltage ... only relevant for MMC1.
 499  *
 500  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 501  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 502  * Some chips, like eMMC ones, use internal transceivers.
 503  */
 504 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 505 {
 506         u32 reg_val = 0;
 507         int ret;
 508
 509         /* Disable the clocks */
 510         clk_disable(host->fclk);
 511         clk_disable(host->iclk);
 512         clk_disable(host->dbclk);
 513
 514         /* Turn the power off */
 515         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 516         if (ret != 0)
 517                 goto err;
 518
 519         /* Turn the power ON with given VDD 1.8 or 3.0v */
 520         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 521         if (ret != 0)
 522                 goto err;
 523
 524         clk_enable(host->fclk);
 525         clk_enable(host->iclk);
 526         clk_enable(host->dbclk);
 527
 528         OMAP_HSMMC_WRITE(host->base, HCTL,
 529                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 530         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 531
 532         /*
 533          * If a MMC dual voltage card is detected, the set_ios fn calls
 534          * this fn with VDD bit set for 1.8V. Upon card removal from the
 535          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 536          *
 537          * Cope with a bit of slop in the range ... per data sheets:
 538          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 539          *    but recommended values are 1.71V to 1.89V
 540          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 541          *    but recommended values are 2.7V to 3.3V
 542          *
 543          * Board setup code shouldn't permit anything very out-of-range.
 544          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 545          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 546          */
 547         if ((1 << vdd) <= MMC_VDD_23_24)
 548                 reg_val |= SDVS18;
 549         else
 550                 reg_val |= SDVS30;
 551
 552         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 553
 554         OMAP_HSMMC_WRITE(host->base, HCTL,
 555                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 556
 557         return 0;
 558 err:
 559         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 560         return ret;
 561 }
 562
 563 /*
 564  * Work Item to notify the core about card insertion/removal
 565  */
 566 static void mmc_omap_detect(struct work_struct *work)
 567 {
 568         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 569                                                 mmc_carddetect_work);
 570         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 571
 572         host->carddetect = slot->card_detect(slot->card_detect_irq);
 573
 574         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 575         if (host->carddetect) {
 576                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 577         } else {
 578                 mmc_omap_reset_controller_fsm(host, SRD);
 579                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 580         }
 581 }
 582
 583 /*
 584  * ISR for handling card insertion and removal
 585  */
 586 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 587 {
 588         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 589
 590         schedule_work(&host->mmc_carddetect_work);
 591
 592         return IRQ_HANDLED;
 593 }
 594
 595 /*
 596  * DMA call back function
 597  */
 598 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 599 {
 600         struct mmc_omap_host *host = data;
 601
 602         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 603                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 604
 605         if (host->dma_ch < 0)
 606                 return;
 607
 608         omap_free_dma(host->dma_ch);
 609         host->dma_ch = -1;
 610         /*
 611          * DMA Callback: run in interrupt context.
 612          * mutex_unlock will through a kernel warning if used.
 613          */
 614         up(&host->sem);
 615 }
 616
 617 /*
 618  * Configure dma src and destination parameters
 619  */
 620 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 621                                 struct mmc_data *data)
 622 {
 623         if (sync_dir == 0) {
 624                 omap_set_dma_dest_params(host->dma_ch, 0,
 625                         OMAP_DMA_AMODE_CONSTANT,
 626                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 627                 omap_set_dma_src_params(host->dma_ch, 0,
 628                         OMAP_DMA_AMODE_POST_INC,
 629                         sg_dma_address(&data->sg[0]), 0, 0);
 630         } else {
 631                 omap_set_dma_src_params(host->dma_ch, 0,
 632                         OMAP_DMA_AMODE_CONSTANT,
 633                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 634                 omap_set_dma_dest_params(host->dma_ch, 0,
 635                         OMAP_DMA_AMODE_POST_INC,
 636                         sg_dma_address(&data->sg[0]), 0, 0);
 637         }
 638         return 0;
 639 }
 640 /*
 641  * Routine to configure and start DMA for the MMC card
 642  */
 643 static int
 644 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 645 {
 646         int sync_dev, sync_dir = 0;
 647         int dma_ch = 0, ret = 0, err = 1;
 648         struct mmc_data *data = req->data;
 649
 650         /*
 651          * If for some reason the DMA transfer is still active,
 652          * we wait for timeout period and free the dma
 653          */
 654         if (host->dma_ch != -1) {
 655                 set_current_state(TASK_UNINTERRUPTIBLE);
 656                 schedule_timeout(100);
 657                 if (down_trylock(&host->sem)) {
 658                         omap_free_dma(host->dma_ch);
 659                         host->dma_ch = -1;
 660                         up(&host->sem);
 661                         return err;
 662                 }
 663         } else {
 664                 if (down_trylock(&host->sem))
 665                         return err;
 666         }
 667
 668         if (!(data->flags & MMC_DATA_WRITE)) {
 669                 host->dma_dir = DMA_FROM_DEVICE;
 670                 if (host->id == OMAP_MMC1_DEVID)
 671                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 672                 else
 673                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 674         } else {
 675                 host->dma_dir = DMA_TO_DEVICE;
 676                 if (host->id == OMAP_MMC1_DEVID)
 677                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 678                 else
 679                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 680         }
 681
 682         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 683                         host, &dma_ch);
 684         if (ret != 0) {
 685                 dev_dbg(mmc_dev(host->mmc),
 686                         "%s: omap_request_dma() failed with %d\n",
 687                         mmc_hostname(host->mmc), ret);
 688                 return ret;
 689         }
 690
 691         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 692                         data->sg_len, host->dma_dir);
 693         host->dma_ch = dma_ch;
 694
 695         if (!(data->flags & MMC_DATA_WRITE))
 696                 mmc_omap_config_dma_param(1, host, data);
 697         else
 698                 mmc_omap_config_dma_param(0, host, data);
 699
 700         if ((data->blksz % 4) == 0)
 701                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 702                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 703                         sync_dev, sync_dir);
 704         else
 705                 /* REVISIT: The MMC buffer increments only when MSB is written.
 706                  * Return error for blksz which is non multiple of four.
 707                  */
 708                 return -EINVAL;
 709
 710         omap_start_dma(dma_ch);
 711         return 0;
 712 }
 713
 714 static void set_data_timeout(struct mmc_omap_host *host,
 715                              struct mmc_request *req)
 716 {
 717         unsigned int timeout, cycle_ns;
 718         uint32_t reg, clkd, dto = 0;
 719
 720         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 721         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 722         if (clkd == 0)
 723                 clkd = 1;
 724
 725         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 726         timeout = req->data->timeout_ns / cycle_ns;
 727         timeout += req->data->timeout_clks;
 728         if (timeout) {
 729                 while ((timeout & 0x80000000) == 0) {
 730                         dto += 1;
 731                         timeout <<= 1;
 732                 }
 733                 dto = 31 - dto;
 734                 timeout <<= 1;
 735                 if (timeout && dto)
 736                         dto += 1;
 737                 if (dto >= 13)
 738                         dto -= 13;
 739                 else
 740                         dto = 0;
 741                 if (dto > 14)
 742                         dto = 14;
 743         }
 744
 745         reg &= ~DTO_MASK;
 746         reg |= dto << DTO_SHIFT;
 747         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 748 }
 749
 750 /*
 751  * Configure block length for MMC/SD cards and initiate the transfer.
 752  */
 753 static int
 754 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 755 {
 756         int ret;
 757         host->data = req->data;
 758
 759         if (req->data == NULL) {
 760                 host->datadir = OMAP_MMC_DATADIR_NONE;
 761                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 762                 return 0;
 763         }
 764
 765         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 766                                         | (req->data->blocks << 16));
 767         set_data_timeout(host, req);
 768
 769         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 770                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 771
 772         if (host->use_dma) {
 773                 ret = mmc_omap_start_dma_transfer(host, req);
 774                 if (ret != 0) {
 775                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 776                         return ret;
 777                 }
 778         }
 779         return 0;
 780 }
 781
 782 /*
 783  * Request function. for read/write operation
 784  */
 785 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 786 {
 787         struct mmc_omap_host *host = mmc_priv(mmc);
 788
 789         WARN_ON(host->mrq != NULL);
 790         host->mrq = req;
 791         mmc_omap_prepare_data(host, req);
 792         mmc_omap_start_command(host, req->cmd, req->data);
 793 }
 794
 795
 796 /* Routine to configure clock values. Exposed API to core */
 797 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 798 {
 799         struct mmc_omap_host *host = mmc_priv(mmc);
 800         u16 dsor = 0;
 801         unsigned long regval;
 802         unsigned long timeout;
 803
 804         switch (ios->power_mode) {
 805         case MMC_POWER_OFF:
 806                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 807                 break;
 808         case MMC_POWER_UP:
 809                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 810                 break;
 811         }
 812
 813         switch (mmc->ios.bus_width) {
 814         case MMC_BUS_WIDTH_4:
 815                 OMAP_HSMMC_WRITE(host->base, HCTL,
 816                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 817                 break;
 818         case MMC_BUS_WIDTH_1:
 819                 OMAP_HSMMC_WRITE(host->base, HCTL,
 820                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 821                 break;
 822         }
 823
 824         if (host->id == OMAP_MMC1_DEVID) {
 825                 /* Only MMC1 can interface at 3V without some flavor
 826                  * of external transceiver; but they all handle 1.8V.
 827                  */
 828                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 829                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 830                                 /*
 831                                  * The mmc_select_voltage fn of the core does
 832                                  * not seem to set the power_mode to
 833                                  * MMC_POWER_UP upon recalculating the voltage.
 834                                  * vdd 1.8v.
 835                                  */
 836                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 837                                         dev_dbg(mmc_dev(host->mmc),
 838                                                 "Switch operation failed\n");
 839                 }
 840         }
 841
 842         if (ios->clock) {
 843                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 844                 if (dsor < 1)
 845                         dsor = 1;
 846
 847                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 848                         dsor++;
 849
 850                 if (dsor > 250)
 851                         dsor = 250;
 852         }
 853         omap_mmc_stop_clock(host);
 854         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 855         regval = regval & ~(CLKD_MASK);
 856         regval = regval | (dsor << 6) | (DTO << 16);
 857         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 858         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 859                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 860
 861         /* Wait till the ICS bit is set */
 862         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 863         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 864                 && time_before(jiffies, timeout))
 865                 msleep(1);
 866
 867         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 868                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 869
 870         if (ios->power_mode == MMC_POWER_ON)
 871                 send_init_stream(host);
 872
 873         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 874                 OMAP_HSMMC_WRITE(host->base, CON,
 875                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 876 }
 877
 878 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 879 {
 880         struct mmc_omap_host *host = mmc_priv(mmc);
 881         struct omap_mmc_platform_data *pdata = host->pdata;
 882
 883         if (!pdata->slots[0].card_detect)
 884                 return -ENOSYS;
 885         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 886 }
 887
 888 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 889 {
 890         struct mmc_omap_host *host = mmc_priv(mmc);
 891         struct omap_mmc_platform_data *pdata = host->pdata;
 892
 893         if (!pdata->slots[0].get_ro)
 894                 return -ENOSYS;
 895         return pdata->slots[0].get_ro(host->dev, 0);
 896 }
 897
 898 static void omap_hsmmc_init(struct mmc_omap_host *host)
 899 {
 900         u32 hctl, capa, value;
 901
 902         /* Only MMC1 supports 3.0V */
 903         if (host->id == OMAP_MMC1_DEVID) {
 904                 hctl = SDVS30;
 905                 capa = VS30 | VS18;
 906         } else {
 907                 hctl = SDVS18;
 908                 capa = VS18;
 909         }
 910
 911         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
 912         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
 913
 914         value = OMAP_HSMMC_READ(host->base, CAPA);
 915         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
 916
 917         /* Set the controller to AUTO IDLE mode */
 918         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
 919         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
 920
 921         /* Set SD bus power bit */
 922         value = OMAP_HSMMC_READ(host->base, HCTL);
 923         OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP);
 924 }
 925
 926 static struct mmc_host_ops mmc_omap_ops = {
 927         .request = omap_mmc_request,
 928         .set_ios = omap_mmc_set_ios,
 929         .get_cd = omap_hsmmc_get_cd,
 930         .get_ro = omap_hsmmc_get_ro,
 931         /* NYET -- enable_sdio_irq */
 932 };
 933
 934 static int __init omap_mmc_probe(struct platform_device *pdev)
 935 {
 936         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 937         struct mmc_host *mmc;
 938         struct mmc_omap_host *host = NULL;
 939         struct resource *res;
 940         int ret = 0, irq;
 941
 942         if (pdata == NULL) {
 943                 dev_err(&pdev->dev, "Platform Data is missing\n");
 944                 return -ENXIO;
 945         }
 946
 947         if (pdata->nr_slots == 0) {
 948                 dev_err(&pdev->dev, "No Slots\n");
 949                 return -ENXIO;
 950         }
 951
 952         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 953         irq = platform_get_irq(pdev, 0);
 954         if (res == NULL || irq < 0)
 955                 return -ENXIO;
 956
 957         res = request_mem_region(res->start, res->end - res->start + 1,
 958                                                         pdev->name);
 959         if (res == NULL)
 960                 return -EBUSY;
 961
 962         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 963         if (!mmc) {
 964                 ret = -ENOMEM;
 965                 goto err;
 966         }
 967
 968         host            = mmc_priv(mmc);
 969         host->mmc       = mmc;
 970         host->pdata     = pdata;
 971         host->dev       = &pdev->dev;
 972         host->use_dma   = 1;
 973         host->dev->dma_mask = &pdata->dma_mask;
 974         host->dma_ch    = -1;
 975         host->irq       = irq;
 976         host->id        = pdev->id;
 977         host->slot_id   = 0;
 978         host->mapbase   = res->start;
 979         host->base      = ioremap(host->mapbase, SZ_4K);
 980
 981         platform_set_drvdata(pdev, host);
 982         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 983
 984         mmc->ops        = &mmc_omap_ops;
 985         mmc->f_min      = 400000;
 986         mmc->f_max      = 52000000;
 987
 988         sema_init(&host->sem, 1);
 989
 990         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 991         if (IS_ERR(host->iclk)) {
 992                 ret = PTR_ERR(host->iclk);
 993                 host->iclk = NULL;
 994                 goto err1;
 995         }
 996         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 997         if (IS_ERR(host->fclk)) {
 998                 ret = PTR_ERR(host->fclk);
 999                 host->fclk = NULL;
1000                 clk_put(host->iclk);
1001                 goto err1;
1002         }
1003
1004         if (clk_enable(host->fclk) != 0) {
1005                 clk_put(host->iclk);
1006                 clk_put(host->fclk);
1007                 goto err1;
1008         }
1009
1010         if (clk_enable(host->iclk) != 0) {
1011                 clk_disable(host->fclk);
1012                 clk_put(host->iclk);
1013                 clk_put(host->fclk);
1014                 goto err1;
1015         }
1016
1017         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1018         /*
1019          * MMC can still work without debounce clock.
1020          */
1021         if (IS_ERR(host->dbclk))
1022                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1023         else
1024                 if (clk_enable(host->dbclk) != 0)
1025                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1026                                                         " clk failed\n");
1027                 else
1028                         host->dbclk_enabled = 1;
1029
1030 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1031         mmc->max_phys_segs = 1;
1032         mmc->max_hw_segs = 1;
1033 #endif
1034         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1035         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1036         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1037         mmc->max_seg_size = mmc->max_req_size;
1038
1039         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1040         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1041
1042         if (pdata->slots[host->slot_id].wires >= 4)
1043                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1044
1045         omap_hsmmc_init(host);
1046
1047         /* Request IRQ for MMC operations */
1048         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1049                         mmc_hostname(mmc), host);
1050         if (ret) {
1051                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1052                 goto err_irq;
1053         }
1054
1055         if (pdata->init != NULL) {
1056                 if (pdata->init(&pdev->dev) != 0) {
1057                         dev_dbg(mmc_dev(host->mmc),
1058                                 "Unable to configure MMC IRQs\n");
1059                         goto err_irq_cd_init;
1060                 }
1061         }
1062
1063         /* Request IRQ for card detect */
1064         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1065                 ret = request_irq(mmc_slot(host).card_detect_irq,
1066                                   omap_mmc_cd_handler,
1067                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1068                                           | IRQF_DISABLED,
1069                                   mmc_hostname(mmc), host);
1070                 if (ret) {
1071                         dev_dbg(mmc_dev(host->mmc),
1072                                 "Unable to grab MMC CD IRQ\n");
1073                         goto err_irq_cd;
1074                 }
1075         }
1076
1077         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1078         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1079
1080         mmc_add_host(mmc);
1081
1082         if (host->pdata->slots[host->slot_id].name != NULL) {
1083                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1084                 if (ret < 0)
1085                         goto err_slot_name;
1086         }
1087         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1088                         host->pdata->slots[host->slot_id].get_cover_state) {
1089                 ret = device_create_file(&mmc->class_dev,
1090                                         &dev_attr_cover_switch);
1091                 if (ret < 0)
1092                         goto err_cover_switch;
1093         }
1094
1095         return 0;
1096
1097 err_cover_switch:
1098         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1099 err_slot_name:
1100         mmc_remove_host(mmc);
1101 err_irq_cd:
1102         free_irq(mmc_slot(host).card_detect_irq, host);
1103 err_irq_cd_init:
1104         free_irq(host->irq, host);
1105 err_irq:
1106         clk_disable(host->fclk);
1107         clk_disable(host->iclk);
1108         clk_put(host->fclk);
1109         clk_put(host->iclk);
1110         if (host->dbclk_enabled) {
1111                 clk_disable(host->dbclk);
1112                 clk_put(host->dbclk);
1113         }
1114
1115 err1:
1116         iounmap(host->base);
1117 err:
1118         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1119         release_mem_region(res->start, res->end - res->start + 1);
1120         if (host)
1121                 mmc_free_host(mmc);
1122         return ret;
1123 }
1124
1125 static int omap_mmc_remove(struct platform_device *pdev)
1126 {
1127         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1128         struct resource *res;
1129
1130         if (host) {
1131                 mmc_remove_host(host->mmc);
1132                 if (host->pdata->cleanup)
1133                         host->pdata->cleanup(&pdev->dev);
1134                 free_irq(host->irq, host);
1135                 if (mmc_slot(host).card_detect_irq)
1136                         free_irq(mmc_slot(host).card_detect_irq, host);
1137                 flush_scheduled_work();
1138
1139                 clk_disable(host->fclk);
1140                 clk_disable(host->iclk);
1141                 clk_put(host->fclk);
1142                 clk_put(host->iclk);
1143                 if (host->dbclk_enabled) {
1144                         clk_disable(host->dbclk);
1145                         clk_put(host->dbclk);
1146                 }
1147
1148                 mmc_free_host(host->mmc);
1149                 iounmap(host->base);
1150         }
1151
1152         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1153         if (res)
1154                 release_mem_region(res->start, res->end - res->start + 1);
1155         platform_set_drvdata(pdev, NULL);
1156
1157         return 0;
1158 }
1159
1160 #ifdef CONFIG_PM
1161 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1162 {
1163         int ret = 0;
1164         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1165
1166         if (host && host->suspended)
1167                 return 0;
1168
1169         if (host) {
1170                 ret = mmc_suspend_host(host->mmc, state);
1171                 if (ret == 0) {
1172                         host->suspended = 1;
1173
1174                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1175                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1176
1177                         if (host->pdata->suspend) {
1178                                 ret = host->pdata->suspend(&pdev->dev,
1179                                                                 host->slot_id);
1180                                 if (ret)
1181                                         dev_dbg(mmc_dev(host->mmc),
1182                                                 "Unable to handle MMC board"
1183                                                 " level suspend\n");
1184                         }
1185
1186                         if (host->id == OMAP_MMC1_DEVID
1187                                         && !(OMAP_HSMMC_READ(host->base, HCTL)
1188                                                         & SDVSDET)) {
1189                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1190                                         OMAP_HSMMC_READ(host->base, HCTL)
1191                                         & SDVSCLR);
1192                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1193                                         OMAP_HSMMC_READ(host->base, HCTL)
1194                                         | SDVS30);
1195                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1196                                         OMAP_HSMMC_READ(host->base, HCTL)
1197                                         | SDBP);
1198                         }
1199
1200                         clk_disable(host->fclk);
1201                         clk_disable(host->iclk);
1202                         clk_disable(host->dbclk);
1203                 }
1204
1205         }
1206         return ret;
1207 }
1208
1209 /* Routine to resume the MMC device */
1210 static int omap_mmc_resume(struct platform_device *pdev)
1211 {
1212         int ret = 0;
1213         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1214
1215         if (host && !host->suspended)
1216                 return 0;
1217
1218         if (host) {
1219
1220                 ret = clk_enable(host->fclk);
1221                 if (ret)
1222                         goto clk_en_err;
1223
1224                 ret = clk_enable(host->iclk);
1225                 if (ret) {
1226                         clk_disable(host->fclk);
1227                         clk_put(host->fclk);
1228                         goto clk_en_err;
1229                 }
1230
1231                 if (clk_enable(host->dbclk) != 0)
1232                         dev_dbg(mmc_dev(host->mmc),
1233                                         "Enabling debounce clk failed\n");
1234
1235                 omap_hsmmc_init(host);
1236
1237                 if (host->pdata->resume) {
1238                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1239                         if (ret)
1240                                 dev_dbg(mmc_dev(host->mmc),
1241                                         "Unmask interrupt failed\n");
1242                 }
1243
1244                 /* Notify the core to resume the host */
1245                 ret = mmc_resume_host(host->mmc);
1246                 if (ret == 0)
1247                         host->suspended = 0;
1248         }
1249
1250         return ret;
1251
1252 clk_en_err:
1253         dev_dbg(mmc_dev(host->mmc),
1254                 "Failed to enable MMC clocks during resume\n");
1255         return ret;
1256 }
1257
1258 #else
1259 #define omap_mmc_suspend        NULL
1260 #define omap_mmc_resume         NULL
1261 #endif
1262
1263 static struct platform_driver omap_mmc_driver = {
1264         .probe          = omap_mmc_probe,
1265         .remove         = omap_mmc_remove,
1266         .suspend        = omap_mmc_suspend,
1267         .resume         = omap_mmc_resume,
1268         .driver         = {
1269                 .name = DRIVER_NAME,
1270                 .owner = THIS_MODULE,
1271         },
1272 };
1273
1274 static int __init omap_mmc_init(void)
1275 {
1276         /* Register the MMC driver */
1277         return platform_driver_register(&omap_mmc_driver);
1278 }
1279
1280 static void __exit omap_mmc_cleanup(void)
1281 {
1282         /* Unregister MMC driver */
1283         platform_driver_unregister(&omap_mmc_driver);
1284 }
1285
1286 module_init(omap_mmc_init);
1287 module_exit(omap_mmc_cleanup);
1288
1289 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1290 MODULE_LICENSE("GPL");
1291 MODULE_ALIAS("platform:" DRIVER_NAME);
1292 MODULE_AUTHOR("Texas Instruments Inc");